[PATCH] D117562: [AMDGPU] Sink immediate VGPR defs if high RP

[Valery Pykhtin via Phabricator via llvm-commits]

vpykhtin added a comment.

> In D117562#3272690 <https://reviews.llvm.org/D117562#3272690>, @vangthao wrote:
> Right, by the time we hit pre-ra scheduler, occupany may already be decreased by MachineLICM and since the scheduler does not currently have any way to decrease register pressure of live-throughs, it would not have any ability to increase occupancy if it was decreased by MachineLICM hoisting from loops. Enforcing an occupancy target for RA will help in this case. Another issue is I believe the scheduler will allow for more VGPR usage as long as it does not decrease occupancy. This may hide some achievable occupancy if we do not handle this before scheduler or make scheduler aware that it can increase occupancy by sinking. I am not sure if disabling MachineLICM altogether in high RP situations would be the best solution here.

So, the idea is to enforce occupancy achieved after scheduling?

BTW, I saw another kind of VGPR usage which can be rematerialized: CSEd addresses "Base + Offset" in some cases can be register consuming.


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https://reviews.llvm.org/D117562