[PATCH] D118215: [RISCV] Add support for matching vwmulsu from fixed vectors.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7269
 
+  // For VWMULSU.vx vd, vs2, rs1. The signed extern op must be vs2,
+  // so if Op0 IsSignExt it can not be a vector extended from scalar.
----------------
Chenbing.Zheng wrote:
> craig.topper wrote:
> > This code doesn't make sense to me. Is it still needed even after removing the `SDNPCommutative` flag?
> > 
> > Once you've identified a VSEXT and VZEXT everything should be fine. Tablegen should only be able to select the splat on zero extend operand.
> I try to delete it after removing the SDNPCommutative flag.  "vwmulsu_vx_v2i16_swap" test failed and  genetate vwmulsu.vx v8, v9, a1.
> This code I add here for blocking combine this stuation in "vwmulsu_vx_v2i16_swap" func.
> Is there any other better way to block it ?
> 
> Optimized vector-legalized selection DAG: %bb.0 'vwmulsu_vx_v2i16_swap:'
> SelectionDAG has 20 nodes:
>   t0: ch = EntryToken
>   t4: i32,ch = CopyFromReg t0, Register:i32 %1
>             t2: i32,ch = CopyFromReg t0, Register:i32 %0
>           t8: v2i8,ch = load<(load (s16) from %ir.x)> t0, t2, undef:i32
>         t25: nxv1i8 = insert_subvector undef:nxv1i8, t8, Constant:i32<0>
>       t28: nxv1i16 = RISCVISD::VZEXT_VL t25, t27, Constant:i32<2>
>           t23: v2i8 = BUILD_VECTOR t4, t4
>         t30: nxv1i8 = insert_subvector undef:nxv1i8, t23, Constant:i32<0>
>       t31: nxv1i16 = RISCVISD::VSEXT_VL t30, t27, Constant:i32<2>
>     t33: nxv1i16 = RISCVISD::MUL_VL t28, t31, t27, Constant:i32<2>
>   t18: ch,glue = CopyToReg t0, Register:nxv1i16 $v8, t33
>   t27: nxv1i1 = RISCVISD::VMSET_VL Constant:i32<2>
>   t19: ch = RISCVISD::RET_FLAG t18, Register:nxv1i16 $v8, t18:1
> 
> After combine:
> 
> SelectionDAG has 18 nodes:
>   t0: ch = EntryToken
>   t4: i32,ch = CopyFromReg t0, Register:i32 %1
>         t23: v2i8 = BUILD_VECTOR t4, t4
>       t30: nxv1i8 = insert_subvector undef:nxv1i8, t23, Constant:i32<0>
>           t2: i32,ch = CopyFromReg t0, Register:i32 %0
>         t8: v2i8,ch = load<(load (s16) from %ir.x)> t0, t2, undef:i32
>       t25: nxv1i8 = insert_subvector undef:nxv1i8, t8, Constant:i32<0>
>       t27: nxv1i1 = RISCVISD::VMSET_VL Constant:i32<2>
>     t35: nxv1i16 = RISCVISD::VWMULSU_VL t30, t25, t27, Constant:i32<2>
>   t18: ch,glue = CopyToReg t0, Register:nxv1i16 $v8, t35
>   t19: ch = RISCVISD::RET_FLAG t18, Register:nxv1i16 $v8, t18:1
With this code removed I get this

```
vwmulsu_vx_v2i16_swap:                  # @vwmulsu_vx_v2i16_swap
        .cfi_startproc
# %bb.0:
        vsetivli        zero, 2, e8, mf8, ta, mu
        vle8.v  v9, (a0)
        vmv.v.x v10, a1
        vwmulsu.vv      v8, v10, v9
        ret
```

That looks correct to me. The splat is done as a separate vmv.v.x.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D118215/new/

https://reviews.llvm.org/D118215