[PATCH] D102310: [RISCV][CodeGen] Implement IR Intrinsic support for K extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:282
     setOperationAction(ISD::BSWAP, XLenVT,
                        Subtarget.hasStdExtZbb() ? Legal : Expand);
   }
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craig.topper wrote:
> You want Zbkb in addition to Zbb here.
Does this line exceed 80 columns?


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td:890
 def : Pat<(i32 (rotl (riscv_grev GPR:$rs1, 24), (i32 16))), (GREVI GPR:$rs1, 8)>;
+} // Predicates = [HasStdExtZbp, IsRV32]
 
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Revert this


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td:892
 
+let Predicates = [HasStdExtZbp, IsRV32] in {
 // We treat rev8 as a separate instruction, so match it directly.
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Revert this


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td:899
 def : Pat<(i32 (riscv_unshfl GPR:$rs1, 15)), (UNZIP_RV32 GPR:$rs1)>;
-} // Predicates = [HasStdExtZbp, IsRV32]
+} // Predicates = [HasStdExtZbpOrZbkb, IsRV32]
 
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Revert this


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  https://reviews.llvm.org/D102310/new/

https://reviews.llvm.org/D102310