[PATCH] D117389: [RISCV] Improve extract_vector_elt for fixed mask registers.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4260
+    if (VecVT.isFixedLengthVector()) {
+      unsigned Nums = VecVT.getVectorMinNumElements();
+      if (Nums >= 8) {
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frasercrmck wrote:
> nit: `Nums` is a little unconventional. `NumElts` or something? You can also use `getVectorNumElements` because we know it's a fixed-length vector.
Done.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll:5
 
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+zfh,+f,+d,+zbs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32ZBS
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+zfh,+f,+d,+zbs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64ZBS
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frasercrmck wrote:
> You'll need to rebase and swap `+experimental-v` for `+v`
Done.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117389/new/

https://reviews.llvm.org/D117389