[PATCH] D117947: [RISCV] Don't allow i64 vector div by constant to use mulh with Zve64x

Yueh-Ting Chen via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Jan 25 09:55:18 PST 2022


This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGb089e4072a01: [RISCV] Don't allow i64 vector div by constant to use mulh with Zve64x (authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117947/new/

https://reviews.llvm.org/D117947

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D117947.402952.patch
Type: text/x-patch
Size: 48990 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220125/b3340b0a/attachment.bin>


More information about the llvm-commits mailing list