[PATCH] D117681: [RISCV] Add the policy operand for some masked RVV ternary IR intrinsics.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.
Herald added a subscriber: pcwang-thead.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:2342
     defm _VS : VPseudoTernary<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>,
-               Sched<[WriteVIRedV, ReadVIRedV, ReadVIRedV, ReadVIRedV, ReadVMask]>;
+               Sched<[WriteVIWRedV, ReadVIWRedV, ReadVIWRedV, ReadVIWRedV, ReadVMask]>;
   }
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Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117681/new/

https://reviews.llvm.org/D117681