[PATCH] D117389: [RISCV] Improve extract_vector_elt for fixed mask registers.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll:272
+; RV32-NEXT:    vmv.x.s a0, v8
+; RV32-NEXT:    srl a0, a0, a1
+; RV32-NEXT:    andi a0, a0, 1
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frasercrmck wrote:
> This doesn't look like it's doing the right thing. We haven't modified the original extract index `a1` at this point so we could be shifting an `i32` right by up to 127 places? Have I missed something?
Here we want to extract the `(idx % 32)`th bit from the GPR, and a1 owns the value of `idx`, so `(idx % 32)` is `a1[4-0]`. And because the shift instruction only uses the 0 - (log2(xlen)-1) bits of rs2, so we actually do not need to get `a1[4-0]`, we could just use a1. So I think here is OK?


Repository:
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  https://reviews.llvm.org/D117389/new/

https://reviews.llvm.org/D117389