[PATCH] D118107: [AArch64] Reassociate integer extending reductions to pairwise addition.

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: jaykang10, samtebbs, labrinea, SjoerdMeijer, david-arm.
Herald added subscribers: hiraditya, kristof.beyls.
dmgreen requested review of this revision.
Herald added a project: LLVM.

Given an (integer) vecreduce, we know the order of the inputs does not matter. We can convert `UADDV(add(zext(extract_lo(x)), zext(extract_hi(x))))` into `UADDV(UADDLP(x))`. This can also happen through an extra add, where we transform `UADDV(add(y, add(zext(extract_lo(x)), zext(extract_hi(x)))))`.

I've made sure the same thing happens signed cases too, which requires adding a new SADDLP node.


https://reviews.llvm.org/D118107

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/aarch64-addv.ll
  llvm/test/CodeGen/AArch64/arm64-vabs.ll
  llvm/test/CodeGen/AArch64/vecreduce-add.ll

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