[PATCH] D115618: [AVR] Optimize int16 airthmetic right shift for shift amount 7/14/15

[Ben Shi via Phabricator via llvm-commits]

benshi001 added a comment.

In D115618#3248072 <https://reviews.llvm.org/D115618#3248072>, @aykevl wrote:

> (just so that this doesn't appear in my review queue anymore)

Thanks for your suggestion. I have done

1. Add a new MIR test to show register state changes.
2. Corrent wrong register state when expanding the ASRW7/ASRW14/ASRW15 pseudo instructions.
3. Add `-verify-machineinstrs` option to the `/llvm/test/CodeGen/AVR/sign-extension.ll`
4. Change the register class of ASRWNRd from `DLDREGS` to `DREGS`.


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https://reviews.llvm.org/D115618