[PATCH] D118057: [AArch64][SVE] Implement missing lowering for extract_subvector for predicates.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/sve-insert-vector.ll:557
+; CHECK-NEXT:    ret
+  %v0 = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv4i1(<vscale x 16 x i1> zeroinitializer, <vscale x 4 x i1> %sv, i64 0)
+  ret <vscale x 16 x i1> %v0
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I don't get this.  `<vscale x 4 x i1>` doesn't have the right layout; it has padding bits in between each value bit.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118057/new/

https://reviews.llvm.org/D118057