[PATCH] D118054: [AArch64][SVE] Mark PFALSE as side-effect free.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

It looks like AArch64TargetLowering::LowerSPLAT_VECTOR is using DAG.getMachineNode in an inappropriate way: generally, in SelectionDAG, we shouldn't be creating Machine nodes before isel (AArch64DAGToDAGISel::Select).  The "proper" construct is to define AArch64ISD::PFALSE, then add a pattern to lower it during isel.

The reason I bring this up is that hasSideEffects is usually inferred from isel patterns.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118054/new/

https://reviews.llvm.org/D118054