[PATCH] D118072: [X86] [CodeView] Add codeview mappings for registers ST0-ST7

[Martin Storsjö via Phabricator via llvm-commits]

mstorsjo created this revision.
mstorsjo added reviewers: aganea, rnk.
Herald added subscribers: pengfei, hiraditya.
mstorsjo requested review of this revision.
Herald added a project: LLVM.

These can end up needed after https://reviews.llvm.org/D116821.

Suggested by @aganea.

This doesn't come with any tests right now - do we need them here, and
are there any suggestion on what kind that should be? (The issue
that originally triggered this probably doesn't reproduce hitting
these register types, as that feature has been disabled/reverted for
now.)


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D118072

Files:
  llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp


Index: llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
===================================================================
--- llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
+++ llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
@@ -111,6 +111,15 @@
 
       {codeview::RegisterId::EFLAGS, X86::EFLAGS},
 
+      {codeview::RegisterId::ST0, X86::ST0},
+      {codeview::RegisterId::ST1, X86::ST1},
+      {codeview::RegisterId::ST2, X86::ST2},
+      {codeview::RegisterId::ST3, X86::ST3},
+      {codeview::RegisterId::ST4, X86::ST4},
+      {codeview::RegisterId::ST5, X86::ST5},
+      {codeview::RegisterId::ST6, X86::ST6},
+      {codeview::RegisterId::ST7, X86::ST7},
+
       {codeview::RegisterId::ST0, X86::FP0},
       {codeview::RegisterId::ST1, X86::FP1},
       {codeview::RegisterId::ST2, X86::FP2},


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