[llvm] c548bc2 - [InstCombine] add tests for icmp with masked mul operand; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 24 12:15:13 PST 2022
Author: Sanjay Patel
Date: 2022-01-24T15:15:03-05:00
New Revision: c548bc258c693df2087eda824308a8da55fd6003
URL: https://github.com/llvm/llvm-project/commit/c548bc258c693df2087eda824308a8da55fd6003
DIFF: https://github.com/llvm/llvm-project/commit/c548bc258c693df2087eda824308a8da55fd6003.diff
LOG: [InstCombine] add tests for icmp with masked mul operand; NFC
More coverage for D114272
Added:
Modified:
llvm/test/Transforms/InstCombine/icmp-mul-and.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/icmp-mul-and.ll b/llvm/test/Transforms/InstCombine/icmp-mul-and.ll
index b15404c0aaa2f..2d63bfac0ffcc 100644
--- a/llvm/test/Transforms/InstCombine/icmp-mul-and.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-mul-and.ll
@@ -1,6 +1,103 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
+declare void @use(i8)
+
+define i1 @mul_mask_pow2_eq0(i8 %x) {
+; CHECK-LABEL: @mul_mask_pow2_eq0(
+; CHECK-NEXT: [[MUL:%.*]] = mul i8 [[X:%.*]], 44
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[MUL]], 4
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[AND]], 0
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %mul = mul i8 %x, 44
+ %and = and i8 %mul, 4
+ %cmp = icmp eq i8 %and, 0
+ ret i1 %cmp
+}
+
+define i1 @mul_mask_pow2_ne0_use1(i8 %x) {
+; CHECK-LABEL: @mul_mask_pow2_ne0_use1(
+; CHECK-NEXT: [[MUL:%.*]] = mul i8 [[X:%.*]], 40
+; CHECK-NEXT: call void @use(i8 [[MUL]])
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[MUL]], 8
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[AND]], 0
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %mul = mul i8 %x, 40
+ call void @use(i8 %mul)
+ %and = and i8 %mul, 8
+ %cmp = icmp ne i8 %and, 0
+ ret i1 %cmp
+}
+
+define i1 @mul_mask_pow2_ne0_use2(i8 %x) {
+; CHECK-LABEL: @mul_mask_pow2_ne0_use2(
+; CHECK-NEXT: [[MUL:%.*]] = mul i8 [[X:%.*]], 40
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[MUL]], 8
+; CHECK-NEXT: call void @use(i8 [[AND]])
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[AND]], 0
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %mul = mul i8 %x, 40
+ %and = and i8 %mul, 8
+ call void @use(i8 %and)
+ %cmp = icmp ne i8 %and, 0
+ ret i1 %cmp
+}
+
+define i1 @mul_mask_pow2_sgt0(i8 %x) {
+; CHECK-LABEL: @mul_mask_pow2_sgt0(
+; CHECK-NEXT: [[MUL:%.*]] = mul i8 [[X:%.*]], 44
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[MUL]], 4
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[AND]], 0
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %mul = mul i8 %x, 44
+ %and = and i8 %mul, 4
+ %cmp = icmp sgt i8 %and, 0
+ ret i1 %cmp
+}
+
+define i1 @mul_mask_fakepow2_ne0(i8 %x) {
+; CHECK-LABEL: @mul_mask_fakepow2_ne0(
+; CHECK-NEXT: [[MUL:%.*]] = mul i8 [[X:%.*]], 44
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[MUL]], 4
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[AND]], 0
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %mul = mul i8 %x, 44
+ %and = and i8 %mul, 5
+ %cmp = icmp ne i8 %and, 0
+ ret i1 %cmp
+}
+
+define i1 @mul_mask_pow2_eq4(i8 %x) {
+; CHECK-LABEL: @mul_mask_pow2_eq4(
+; CHECK-NEXT: [[MUL:%.*]] = mul i8 [[X:%.*]], 44
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[MUL]], 4
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[AND]], 0
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %mul = mul i8 %x, 44
+ %and = and i8 %mul, 4
+ %cmp = icmp eq i8 %and, 4
+ ret i1 %cmp
+}
+
+define i1 @mul_mask_notpow2_ne(i8 %x) {
+; CHECK-LABEL: @mul_mask_notpow2_ne(
+; CHECK-NEXT: [[MUL:%.*]] = mul i8 [[X:%.*]], 60
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[MUL]], 12
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[AND]], 0
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %mul = mul i8 %x, 60
+ %and = and i8 %mul, 12
+ %cmp = icmp ne i8 %and, 0
+ ret i1 %cmp
+}
+
define i1 @pr40493(i32 %area) {
; CHECK-LABEL: @pr40493(
; CHECK-NEXT: entry:
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