[llvm] c27f8fb - [AMDGPU] Remove cndmask from readsExecAsData
Stanislav Mekhanoshin via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 24 11:24:55 PST 2022
Author: Stanislav Mekhanoshin
Date: 2022-01-24T11:24:47-08:00
New Revision: c27f8fb96882ee8c684d03068836cf610d4f0640
URL: https://github.com/llvm/llvm-project/commit/c27f8fb96882ee8c684d03068836cf610d4f0640
DIFF: https://github.com/llvm/llvm-project/commit/c27f8fb96882ee8c684d03068836cf610d4f0640.diff
LOG: [AMDGPU] Remove cndmask from readsExecAsData
Differential Revision: https://reviews.llvm.org/D117909
Added:
Modified:
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/test/CodeGen/AMDGPU/licm-valu.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 3ac04ee717dea..f89f109d0d3a2 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -138,11 +138,6 @@ static bool readsExecAsData(const MachineInstr &MI) {
default:
break;
case AMDGPU::V_READFIRSTLANE_B32:
- case AMDGPU::V_CNDMASK_B64_PSEUDO:
- case AMDGPU::V_CNDMASK_B32_dpp:
- case AMDGPU::V_CNDMASK_B32_e32:
- case AMDGPU::V_CNDMASK_B32_e64:
- case AMDGPU::V_CNDMASK_B32_sdwa:
return true;
}
diff --git a/llvm/test/CodeGen/AMDGPU/licm-valu.mir b/llvm/test/CodeGen/AMDGPU/licm-valu.mir
index 45a050cffde9c..0bf2c7c2bc3ba 100644
--- a/llvm/test/CodeGen/AMDGPU/licm-valu.mir
+++ b/llvm/test/CodeGen/AMDGPU/licm-valu.mir
@@ -99,147 +99,3 @@ body: |
bb.2:
S_ENDPGM 0
...
----
-name: no_hoist_cndmask_e64
-tracksRegLiveness: true
-body: |
- ; GCN-LABEL: name: no_hoist_cndmask_e64
- ; GCN: bb.0:
- ; GCN-NEXT: successors: %bb.1(0x80000000)
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
- ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
- ; GCN-NEXT: S_BRANCH %bb.1
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: bb.1:
- ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[DEF]], 0, [[DEF]], [[DEF1]], implicit $exec
- ; GCN-NEXT: $exec = S_OR_B64 $exec, 1, implicit-def $scc
- ; GCN-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec
- ; GCN-NEXT: S_BRANCH %bb.2
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: bb.2:
- ; GCN-NEXT: S_ENDPGM 0
- bb.0:
- %0:vgpr_32 = IMPLICIT_DEF
- %1:sreg_64_xexec = IMPLICIT_DEF
- S_BRANCH %bb.1
-
- bb.1:
- %2:vgpr_32 = V_CNDMASK_B32_e64 0, %0, 0, %0, %1, implicit $exec
- $exec = S_OR_B64 $exec, 1, implicit-def $scc
- S_CBRANCH_EXECNZ %bb.1, implicit $exec
- S_BRANCH %bb.2
-
- bb.2:
- S_ENDPGM 0
-...
----
-name: no_hoist_cndmask_e32
-tracksRegLiveness: true
-body: |
- ; GCN-LABEL: name: no_hoist_cndmask_e32
- ; GCN: bb.0:
- ; GCN-NEXT: successors: %bb.1(0x80000000)
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
- ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
- ; GCN-NEXT: S_BRANCH %bb.1
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: bb.1:
- ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[V_CNDMASK_B32_e32_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e32 [[DEF]], [[DEF]], implicit undef $vcc, implicit $exec
- ; GCN-NEXT: $exec = S_OR_B64 $exec, 1, implicit-def $scc
- ; GCN-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec
- ; GCN-NEXT: S_BRANCH %bb.2
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: bb.2:
- ; GCN-NEXT: S_ENDPGM 0
- bb.0:
- %0:vgpr_32 = IMPLICIT_DEF
- %1:sreg_64_xexec = IMPLICIT_DEF
- S_BRANCH %bb.1
-
- bb.1:
- %2:vgpr_32 = V_CNDMASK_B32_e32 %0, %0, implicit undef $vcc, implicit $exec
- $exec = S_OR_B64 $exec, 1, implicit-def $scc
- S_CBRANCH_EXECNZ %bb.1, implicit $exec
- S_BRANCH %bb.2
-
- bb.2:
- S_ENDPGM 0
-...
----
-name: no_hoist_cndmask_dpp
-tracksRegLiveness: true
-body: |
- ; GCN-LABEL: name: no_hoist_cndmask_dpp
- ; GCN: bb.0:
- ; GCN-NEXT: successors: %bb.1(0x80000000)
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
- ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
- ; GCN-NEXT: S_BRANCH %bb.1
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: bb.1:
- ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[V_CNDMASK_B32_dpp:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_dpp [[DEF]], 0, [[DEF]], 0, [[DEF]], 1, 15, 15, 10, implicit $exec, implicit undef $vcc
- ; GCN-NEXT: $exec = S_OR_B64 $exec, 1, implicit-def $scc
- ; GCN-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec
- ; GCN-NEXT: S_BRANCH %bb.2
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: bb.2:
- ; GCN-NEXT: S_ENDPGM 0
- bb.0:
- %0:vgpr_32 = IMPLICIT_DEF
- %1:sreg_64_xexec = IMPLICIT_DEF
- S_BRANCH %bb.1
-
- bb.1:
- %2:vgpr_32 = V_CNDMASK_B32_dpp %0:vgpr_32, 0, %0:vgpr_32, 0, %0:vgpr_32, 1, 15, 15, 10, implicit $exec, implicit undef $vcc
- $exec = S_OR_B64 $exec, 1, implicit-def $scc
- S_CBRANCH_EXECNZ %bb.1, implicit $exec
- S_BRANCH %bb.2
-
- bb.2:
- S_ENDPGM 0
-...
----
-name: no_hoist_cndmask_sdwa
-tracksRegLiveness: true
-body: |
- ; GCN-LABEL: name: no_hoist_cndmask_sdwa
- ; GCN: bb.0:
- ; GCN-NEXT: successors: %bb.1(0x80000000)
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
- ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
- ; GCN-NEXT: S_BRANCH %bb.1
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: bb.1:
- ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[V_CNDMASK_B32_sdwa:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_sdwa 0, [[DEF]], 0, [[DEF]], 0, 0, 0, 0, 0, implicit $exec, implicit undef $vcc
- ; GCN-NEXT: $exec = S_OR_B64 $exec, 1, implicit-def $scc
- ; GCN-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec
- ; GCN-NEXT: S_BRANCH %bb.2
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: bb.2:
- ; GCN-NEXT: S_ENDPGM 0
- bb.0:
- %0:vgpr_32 = IMPLICIT_DEF
- %1:sreg_64_xexec = IMPLICIT_DEF
- S_BRANCH %bb.1
-
- bb.1:
- %2:vgpr_32 = V_CNDMASK_B32_sdwa 0, %0:vgpr_32, 0, %0:vgpr_32, 0, 0, 0, 0, 0, implicit $exec, implicit undef $vcc
- $exec = S_OR_B64 $exec, 1, implicit-def $scc
- S_CBRANCH_EXECNZ %bb.1, implicit $exec
- S_BRANCH %bb.2
-
- bb.2:
- S_ENDPGM 0
-...
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