[PATCH] D102310: [RISCV][CodeGen] Implement IR Intrinsic support for K extension

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Jan 24 07:53:55 PST 2022


craig.topper added inline comments.
Herald added a subscriber: pcwang-thead.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:259
 
-  if (Subtarget.hasStdExtZbp()) {
+  if (Subtarget.hasStdExtZbp() || Subtarget.hasStdExtZbkb()) {
     // Custom lower bswap/bitreverse so we can convert them to GREVI to enable
----------------
This should be done in the else block where hasStdExtZbb() is handled. Zbp is for GREVI.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2427
     // Convert BSWAP/BITREVERSE to GREVI to enable GREVI combinining.
-    assert(Subtarget.hasStdExtZbp() && "Unexpected custom legalisation");
+    assert((Subtarget.hasStdExtZbp() || Subtarget.hasStdExtZbkb()) &&
+           "Unexpected custom legalisation");
----------------
This should not be needed with the other change.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZk.td:24
 
-def rnum : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<4>(Imm);}]> {
+def rnum : Operand<i32>, TImmLeaf<i32, [{return isInt<4>(Imm);}]> {
   let ParserMatchClass = RnumArg;
----------------
This needs to be rebased on the current Zk patch.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZk.td:211
+let Predicates = [HasStdExtZbkb] in {
+def : PatGprGpr<rotr, ROR_K>;
+def : PatGprGpr<rotl, ROL_K>;
----------------
There are no _K instructions in the most recent Zk patches.

All Zb* related changes should be in RISCVInstrInfoZb.td


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D102310/new/

https://reviews.llvm.org/D102310



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