[PATCH] D118036: [PowerPC] Add the Power10 XS[MAX|MIN]CQP instruction.

[Ting Wang via Phabricator via llvm-commits]

tingwang created this revision.
tingwang added reviewers: stefanp, nemanjai, jsji, shchenz, PowerPC.
tingwang added a project: LLVM.
Herald added subscribers: kbarton, hiraditya.
tingwang requested review of this revision.
Herald added a subscriber: llvm-commits.

Add the Power 10 instruction XS[MAX|MIN]CQP.

This will enable the base instructions required by https://reviews.llvm.org/D117006. TD file changes took from wyvern_dev, and encodings verified manually.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D118036

Files:
  llvm/lib/Target/PowerPC/P10InstrResources.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
  llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s


Index: llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
===================================================================
--- llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
+++ llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
@@ -936,6 +936,12 @@
 # CHECK-BE: xscvsqqp 8, 28                        # encoding: [0xfd,0x0b,0xe6,0x88]
 # CHECK-LE: xscvsqqp 8, 28                        # encoding: [0x88,0xe6,0x0b,0xfd]
             xscvsqqp 8, 28
+# CHECK-BE: xsmaxcqp 2, 2, 3                      # encoding: [0xfc,0x42,0x1d,0x48]
+# CHECK-LE: xsmaxcqp 2, 2, 3                      # encoding: [0x48,0x1d,0x42,0xfc]
+            xsmaxcqp 2, 2, 3
+# CHECK-BE: xsmincqp 2, 2, 3                      # encoding: [0xfc,0x42,0x1d,0xc8]
+# CHECK-LE: xsmincqp 2, 2, 3                      # encoding: [0xc8,0x1d,0x42,0xfc]
+            xsmincqp 2, 2, 3
 # CHECK-BE: vstribr 2, 2                          # encoding: [0x10,0x41,0x10,0x0d]
 # CHECK-LE: vstribr 2, 2                          # encoding: [0x0d,0x10,0x41,0x10]
             vstribr 2, 2
Index: llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
===================================================================
--- llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
+++ llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
@@ -738,6 +738,12 @@
 # CHECK: xscvsqqp 8, 28
 0xfd 0xb 0xe6 0x88
 
+# CHECK: xsmaxcqp 2, 2, 3
+0xfc 0x42 0x1d 0x48
+
+# CHECK: xsmincqp 2, 2, 3
+0xfc 0x42 0x1d 0xc8
+
 # CHECK: vstribr 2, 2
 0x10 0x41 0x10 0x0d
 
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -2393,6 +2393,8 @@
   def XSCVQPSQZ : X_VT5_XO5_VB5<63, 8, 836, "xscvqpsqz", []>;
   def XSCVUQQP : X_VT5_XO5_VB5<63, 3, 836, "xscvuqqp", []>;
   def XSCVSQQP : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>;
+  def XSMAXCQP : X_VT5_VA5_VB5<63, 676, "xsmaxcqp", []>;
+  def XSMINCQP : X_VT5_VA5_VB5<63, 740, "xsmincqp", []>;
 }
 
 let Predicates = [IsISA3_1, HasVSX] in {
Index: llvm/lib/Target/PowerPC/P10InstrResources.td
===================================================================
--- llvm/lib/Target/PowerPC/P10InstrResources.td
+++ llvm/lib/Target/PowerPC/P10InstrResources.td
@@ -619,6 +619,8 @@
     XSCMPEXPQP,
     XSCMPOQP,
     XSCMPUQP,
+    XSMAXCQP,
+    XSMINCQP,
     XSTSTDCQP,
     XXGENPCVBM
 )>;


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