[llvm] e7926e8 - [RISCV] Match VF variants for masked VFRDIV/VFRSUB
Fraser Cormack via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 24 03:10:04 PST 2022
Author: Fraser Cormack
Date: 2022-01-24T10:59:43Z
New Revision: e7926e8d972e8129d4b64e10a38719b066a526be
URL: https://github.com/llvm/llvm-project/commit/e7926e8d972e8129d4b64e10a38719b066a526be
DIFF: https://github.com/llvm/llvm-project/commit/e7926e8d972e8129d4b64e10a38719b066a526be.diff
LOG: [RISCV] Match VF variants for masked VFRDIV/VFRSUB
This patch follows up on D117697 to help the simple binary operations
behave similarly in the presence of masks.
It also enables CGP sinking support for vp.fdiv and vp.fsub intrinsics,
now that VFRDIV and VFRSUB are consistently matched with a LHS splat for
masked and unmasked variants.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D117783
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 411191343cf04..5073fe66c15a9 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1272,9 +1272,7 @@ bool RISCVTargetLowering::shouldSinkOperands(
case Intrinsic::vp_or:
case Intrinsic::vp_xor:
case Intrinsic::vp_fadd:
- case Intrinsic::vp_fsub:
case Intrinsic::vp_fmul:
- case Intrinsic::vp_fdiv:
case Intrinsic::vp_shl:
case Intrinsic::vp_lshr:
case Intrinsic::vp_ashr:
@@ -1283,9 +1281,11 @@ bool RISCVTargetLowering::shouldSinkOperands(
case Intrinsic::vp_urem:
case Intrinsic::vp_srem:
return Operand == 1;
- // ... the one exception is vp.sub which has explicit patterns for both
- // LHS and RHS (as vrsub).
+ // ... with the exception of vp.sub/vp.fsub/vp.fdiv, which have
+ // explicit patterns for both LHS and RHS (as 'vr' versions).
case Intrinsic::vp_sub:
+ case Intrinsic::vp_fsub:
+ case Intrinsic::vp_fdiv:
return Operand == 0 || Operand == 1;
default:
return false;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 7b556174bbf0c..9e47cb80349bf 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -404,7 +404,7 @@ multiclass VPatBinaryFPVL_VV_VF<SDNode vop, string instruction_name> {
}
multiclass VPatBinaryFPVL_R_VF<SDNode vop, string instruction_name> {
- foreach fvti = AllFloatVectors in
+ foreach fvti = AllFloatVectors in {
def : Pat<(fvti.Vector (vop (SplatFPOp fvti.ScalarRegClass:$rs2),
fvti.RegClass:$rs1,
(fvti.Mask true_mask),
@@ -412,6 +412,15 @@ multiclass VPatBinaryFPVL_R_VF<SDNode vop, string instruction_name> {
(!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX)
fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2,
GPR:$vl, fvti.Log2SEW)>;
+ def : Pat<(fvti.Vector (vop (SplatFPOp fvti.ScalarRegClass:$rs2),
+ fvti.RegClass:$rs1,
+ (fvti.Mask V0),
+ VLOpFrag)),
+ (!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK")
+ (fvti.Vector (IMPLICIT_DEF)),
+ fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2,
+ (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;
+ }
}
multiclass VPatIntegerSetCCVL_VV<VTypeInfo vti, string instruction_name,
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
index c7a4364b8d497..b902ff1a03d56 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
@@ -9,10 +9,8 @@ declare <2 x half> @llvm.vp.fdiv.v2f16(<2 x half>, <2 x half>, <2 x i1>, i32)
define <2 x half> @vfrdiv_vf_v2f16(<2 x half> %va, half %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfrdiv_vf_v2f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vfrdiv.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x half> undef, half %b, i32 0
%vb = shufflevector <2 x half> %elt.head, <2 x half> undef, <2 x i32> zeroinitializer
@@ -39,10 +37,8 @@ declare <4 x half> @llvm.vp.fdiv.v4f16(<4 x half>, <4 x half>, <4 x i1>, i32)
define <4 x half> @vfrdiv_vf_v4f16(<4 x half> %va, half %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfrdiv_vf_v4f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vfrdiv.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x half> undef, half %b, i32 0
%vb = shufflevector <4 x half> %elt.head, <4 x half> undef, <4 x i32> zeroinitializer
@@ -69,10 +65,8 @@ declare <8 x half> @llvm.vp.fdiv.v8f16(<8 x half>, <8 x half>, <8 x i1>, i32)
define <8 x half> @vfrdiv_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfrdiv_vf_v8f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vfrdiv.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x half> undef, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> undef, <8 x i32> zeroinitializer
@@ -99,10 +93,8 @@ declare <16 x half> @llvm.vp.fdiv.v16f16(<16 x half>, <16 x half>, <16 x i1>, i3
define <16 x half> @vfrdiv_vf_v16f16(<16 x half> %va, half %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfrdiv_vf_v16f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v10, v8, v0.t
+; CHECK-NEXT: vfrdiv.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <16 x half> undef, half %b, i32 0
%vb = shufflevector <16 x half> %elt.head, <16 x half> undef, <16 x i32> zeroinitializer
@@ -129,10 +121,8 @@ declare <2 x float> @llvm.vp.fdiv.v2f32(<2 x float>, <2 x float>, <2 x i1>, i32)
define <2 x float> @vfrdiv_vf_v2f32(<2 x float> %va, float %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfrdiv_vf_v2f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vfrdiv.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x float> undef, float %b, i32 0
%vb = shufflevector <2 x float> %elt.head, <2 x float> undef, <2 x i32> zeroinitializer
@@ -159,10 +149,8 @@ declare <4 x float> @llvm.vp.fdiv.v4f32(<4 x float>, <4 x float>, <4 x i1>, i32)
define <4 x float> @vfrdiv_vf_v4f32(<4 x float> %va, float %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfrdiv_vf_v4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vfrdiv.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x float> undef, float %b, i32 0
%vb = shufflevector <4 x float> %elt.head, <4 x float> undef, <4 x i32> zeroinitializer
@@ -189,10 +177,8 @@ declare <8 x float> @llvm.vp.fdiv.v8f32(<8 x float>, <8 x float>, <8 x i1>, i32)
define <8 x float> @vfrdiv_vf_v8f32(<8 x float> %va, float %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfrdiv_vf_v8f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v10, v8, v0.t
+; CHECK-NEXT: vfrdiv.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x float> undef, float %b, i32 0
%vb = shufflevector <8 x float> %elt.head, <8 x float> undef, <8 x i32> zeroinitializer
@@ -219,10 +205,8 @@ declare <16 x float> @llvm.vp.fdiv.v16f32(<16 x float>, <16 x float>, <16 x i1>,
define <16 x float> @vfrdiv_vf_v16f32(<16 x float> %va, float %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfrdiv_vf_v16f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v12, v8, v0.t
+; CHECK-NEXT: vfrdiv.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <16 x float> undef, float %b, i32 0
%vb = shufflevector <16 x float> %elt.head, <16 x float> undef, <16 x i32> zeroinitializer
@@ -249,10 +233,8 @@ declare <2 x double> @llvm.vp.fdiv.v2f64(<2 x double>, <2 x double>, <2 x i1>, i
define <2 x double> @vfrdiv_vf_v2f64(<2 x double> %va, double %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfrdiv_vf_v2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vfrdiv.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x double> undef, double %b, i32 0
%vb = shufflevector <2 x double> %elt.head, <2 x double> undef, <2 x i32> zeroinitializer
@@ -279,10 +261,8 @@ declare <4 x double> @llvm.vp.fdiv.v4f64(<4 x double>, <4 x double>, <4 x i1>, i
define <4 x double> @vfrdiv_vf_v4f64(<4 x double> %va, double %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfrdiv_vf_v4f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v10, v8, v0.t
+; CHECK-NEXT: vfrdiv.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x double> undef, double %b, i32 0
%vb = shufflevector <4 x double> %elt.head, <4 x double> undef, <4 x i32> zeroinitializer
@@ -309,10 +289,8 @@ declare <8 x double> @llvm.vp.fdiv.v8f64(<8 x double>, <8 x double>, <8 x i1>, i
define <8 x double> @vfrdiv_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfrdiv_vf_v8f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v12, v8, v0.t
+; CHECK-NEXT: vfrdiv.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x double> undef, double %b, i32 0
%vb = shufflevector <8 x double> %elt.head, <8 x double> undef, <8 x i32> zeroinitializer
@@ -339,10 +317,8 @@ declare <16 x double> @llvm.vp.fdiv.v16f64(<16 x double>, <16 x double>, <16 x i
define <16 x double> @vfrdiv_vf_v16f64(<16 x double> %va, double %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfrdiv_vf_v16f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v16, v8, v0.t
+; CHECK-NEXT: vfrdiv.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <16 x double> undef, double %b, i32 0
%vb = shufflevector <16 x double> %elt.head, <16 x double> undef, <16 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
index bdf7c6601d8d8..dfb436437e765 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
@@ -9,10 +9,8 @@ declare <2 x half> @llvm.vp.fsub.v2f16(<2 x half>, <2 x half>, <2 x i1>, i32)
define <2 x half> @vfrsub_vf_v2f16(<2 x half> %va, half %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfrsub_vf_v2f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vfrsub.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x half> undef, half %b, i32 0
%vb = shufflevector <2 x half> %elt.head, <2 x half> undef, <2 x i32> zeroinitializer
@@ -39,10 +37,8 @@ declare <4 x half> @llvm.vp.fsub.v4f16(<4 x half>, <4 x half>, <4 x i1>, i32)
define <4 x half> @vfrsub_vf_v4f16(<4 x half> %va, half %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfrsub_vf_v4f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vfrsub.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x half> undef, half %b, i32 0
%vb = shufflevector <4 x half> %elt.head, <4 x half> undef, <4 x i32> zeroinitializer
@@ -69,10 +65,8 @@ declare <8 x half> @llvm.vp.fsub.v8f16(<8 x half>, <8 x half>, <8 x i1>, i32)
define <8 x half> @vfrsub_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfrsub_vf_v8f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vfrsub.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x half> undef, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> undef, <8 x i32> zeroinitializer
@@ -99,10 +93,8 @@ declare <16 x half> @llvm.vp.fsub.v16f16(<16 x half>, <16 x half>, <16 x i1>, i3
define <16 x half> @vfrsub_vf_v16f16(<16 x half> %va, half %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfrsub_vf_v16f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v10, v8, v0.t
+; CHECK-NEXT: vfrsub.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <16 x half> undef, half %b, i32 0
%vb = shufflevector <16 x half> %elt.head, <16 x half> undef, <16 x i32> zeroinitializer
@@ -129,10 +121,8 @@ declare <2 x float> @llvm.vp.fsub.v2f32(<2 x float>, <2 x float>, <2 x i1>, i32)
define <2 x float> @vfrsub_vf_v2f32(<2 x float> %va, float %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfrsub_vf_v2f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vfrsub.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x float> undef, float %b, i32 0
%vb = shufflevector <2 x float> %elt.head, <2 x float> undef, <2 x i32> zeroinitializer
@@ -159,10 +149,8 @@ declare <4 x float> @llvm.vp.fsub.v4f32(<4 x float>, <4 x float>, <4 x i1>, i32)
define <4 x float> @vfrsub_vf_v4f32(<4 x float> %va, float %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfrsub_vf_v4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vfrsub.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x float> undef, float %b, i32 0
%vb = shufflevector <4 x float> %elt.head, <4 x float> undef, <4 x i32> zeroinitializer
@@ -189,10 +177,8 @@ declare <8 x float> @llvm.vp.fsub.v8f32(<8 x float>, <8 x float>, <8 x i1>, i32)
define <8 x float> @vfrsub_vf_v8f32(<8 x float> %va, float %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfrsub_vf_v8f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v10, v8, v0.t
+; CHECK-NEXT: vfrsub.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x float> undef, float %b, i32 0
%vb = shufflevector <8 x float> %elt.head, <8 x float> undef, <8 x i32> zeroinitializer
@@ -219,10 +205,8 @@ declare <16 x float> @llvm.vp.fsub.v16f32(<16 x float>, <16 x float>, <16 x i1>,
define <16 x float> @vfrsub_vf_v16f32(<16 x float> %va, float %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfrsub_vf_v16f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v12, v8, v0.t
+; CHECK-NEXT: vfrsub.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <16 x float> undef, float %b, i32 0
%vb = shufflevector <16 x float> %elt.head, <16 x float> undef, <16 x i32> zeroinitializer
@@ -249,10 +233,8 @@ declare <2 x double> @llvm.vp.fsub.v2f64(<2 x double>, <2 x double>, <2 x i1>, i
define <2 x double> @vfrsub_vf_v2f64(<2 x double> %va, double %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfrsub_vf_v2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vfrsub.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x double> undef, double %b, i32 0
%vb = shufflevector <2 x double> %elt.head, <2 x double> undef, <2 x i32> zeroinitializer
@@ -279,10 +261,8 @@ declare <4 x double> @llvm.vp.fsub.v4f64(<4 x double>, <4 x double>, <4 x i1>, i
define <4 x double> @vfrsub_vf_v4f64(<4 x double> %va, double %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfrsub_vf_v4f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v10, v8, v0.t
+; CHECK-NEXT: vfrsub.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x double> undef, double %b, i32 0
%vb = shufflevector <4 x double> %elt.head, <4 x double> undef, <4 x i32> zeroinitializer
@@ -309,10 +289,8 @@ declare <8 x double> @llvm.vp.fsub.v8f64(<8 x double>, <8 x double>, <8 x i1>, i
define <8 x double> @vfrsub_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfrsub_vf_v8f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v12, v8, v0.t
+; CHECK-NEXT: vfrsub.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x double> undef, double %b, i32 0
%vb = shufflevector <8 x double> %elt.head, <8 x double> undef, <8 x i32> zeroinitializer
@@ -339,10 +317,8 @@ declare <16 x double> @llvm.vp.fsub.v16f64(<16 x double>, <16 x double>, <16 x i
define <16 x double> @vfrsub_vf_v16f64(<16 x double> %va, double %b, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfrsub_vf_v16f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v16, v8, v0.t
+; CHECK-NEXT: vfrsub.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <16 x double> undef, double %b, i32 0
%vb = shufflevector <16 x double> %elt.head, <16 x double> undef, <16 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
index e902e1cd577a8..5bfa79e02e437 100644
--- a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
@@ -3364,22 +3364,19 @@ for.cond.cleanup: ; preds = %vector.body
ret void
}
-; FIXME: vfrdiv.vf doesn't match against masked instructions
-
define void @sink_splat_vp_frdiv(float* nocapture %a, float %x, <4 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: sink_splat_vp_frdiv:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a1
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v8, ft0
; CHECK-NEXT: li a1, 1024
; CHECK-NEXT: .LBB56_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
-; CHECK-NEXT: vfdiv.vv v9, v8, v9, v0.t
+; CHECK-NEXT: vfrdiv.vf v8, v8, ft0, v0.t
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vse32.v v9, (a0)
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: addi a1, a1, -4
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: bnez a1, .LBB56_1
@@ -3490,22 +3487,19 @@ for.cond.cleanup: ; preds = %vector.body
declare <4 x float> @llvm.vp.frsub.v4i32(<4 x float>, <4 x float>, <4 x i1>, i32)
-; FIXME: vfrsub.vf doesn't match against masked instructions
-
define void @sink_splat_vp_frsub(float* nocapture %a, float %x, <4 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: sink_splat_vp_frsub:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a1
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v8, ft0
; CHECK-NEXT: li a1, 1024
; CHECK-NEXT: .LBB59_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
-; CHECK-NEXT: vfsub.vv v9, v8, v9, v0.t
+; CHECK-NEXT: vfrsub.vf v8, v8, ft0, v0.t
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vse32.v v9, (a0)
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: addi a1, a1, -4
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: bnez a1, .LBB59_1
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