[llvm] 906ebd5 - [AMDGPU][GlobalISel] Regenerate checks in inst-select-*ext.mir
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 24 02:27:21 PST 2022
Author: Jay Foad
Date: 2022-01-24T10:16:51Z
New Revision: 906ebd5830e6053b50c52bf098e3586b567e8499
URL: https://github.com/llvm/llvm-project/commit/906ebd5830e6053b50c52bf098e3586b567e8499
DIFF: https://github.com/llvm/llvm-project/commit/906ebd5830e6053b50c52bf098e3586b567e8499.diff
LOG: [AMDGPU][GlobalISel] Regenerate checks in inst-select-*ext.mir
Added:
Modified:
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
index dcad0a85e8e0..3ae9735d11b9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
@@ -13,7 +13,7 @@ body: |
; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: $sgpr0 = COPY [[COPY]]
+ ; GCN-NEXT: $sgpr0 = COPY [[COPY]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0
%2:sgpr(s32) = G_ANYEXT %1
@@ -22,7 +22,7 @@ body: |
...
---
-name: anyext_sgpr_s32_to_sgpr_s64
+name: anyext_sgpr_s32_to_sgpr_s64
legalized: true
regBankSelected: true
tracksRegLiveness: true
@@ -32,10 +32,11 @@ body: |
; GCN-LABEL: name: anyext_sgpr_s32_to_sgpr_s64
; GCN: liveins: $sgpr0
- ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
- ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
- ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
+ ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s64) = G_ANYEXT %0
S_ENDPGM 0, implicit %1
@@ -43,7 +44,7 @@ body: |
...
---
-name: anyext_sgpr_s16_to_sgpr_s64
+name: anyext_sgpr_s16_to_sgpr_s64
legalized: true
regBankSelected: true
tracksRegLiveness: true
@@ -53,10 +54,11 @@ body: |
; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s64
; GCN: liveins: $sgpr0
- ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
- ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
- ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
+ ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0
%2:sgpr(s64) = G_ANYEXT %1
@@ -65,7 +67,7 @@ body: |
...
---
-name: anyext_vgpr_s32_to_vgpr_s64
+name: anyext_vgpr_s32_to_vgpr_s64
legalized: true
regBankSelected: true
tracksRegLiveness: true
@@ -75,10 +77,11 @@ body: |
; GCN-LABEL: name: anyext_vgpr_s32_to_vgpr_s64
; GCN: liveins: $vgpr0
- ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
- ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
- ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
+ ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s64) = G_ANYEXT %0
S_ENDPGM 0, implicit %1
@@ -86,7 +89,7 @@ body: |
...
---
-name: anyext_vgpr_s16_to_vgpr_s64
+name: anyext_vgpr_s16_to_vgpr_s64
legalized: true
regBankSelected: true
tracksRegLiveness: true
@@ -96,10 +99,11 @@ body: |
; GCN-LABEL: name: anyext_vgpr_s16_to_vgpr_s64
; GCN: liveins: $vgpr0
- ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
- ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
- ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
+ ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s64) = G_ANYEXT %1
@@ -134,7 +138,7 @@ body: |
; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: $sgpr0 = COPY [[COPY]]
+ ; GCN-NEXT: $sgpr0 = COPY [[COPY]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s1) = G_TRUNC %0
%2:sgpr(s32) = G_ANYEXT %1
@@ -152,7 +156,7 @@ body: |
; GCN-LABEL: name: anyext_vgpr_s1_to_vgpr_s32
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GCN: $vgpr0 = COPY [[COPY]]
+ ; GCN-NEXT: $vgpr0 = COPY [[COPY]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s1) = G_TRUNC %0
%2:vgpr(s32) = G_ANYEXT %1
@@ -170,7 +174,7 @@ body: |
; GCN-LABEL: name: anyext_sgpr_s1_to_vgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: $sgpr0 = COPY [[COPY]]
+ ; GCN-NEXT: $sgpr0 = COPY [[COPY]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s1) = G_TRUNC %0
%2:sgpr(s32) = G_ANYEXT %1
@@ -188,7 +192,7 @@ body: |
; GCN-LABEL: name: anyext_vgpr_s16_to_vgpr_s32
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GCN: $vgpr0 = COPY [[COPY]]
+ ; GCN-NEXT: $vgpr0 = COPY [[COPY]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s32) = G_ANYEXT %1
@@ -209,7 +213,7 @@ body: |
; GCN-LABEL: name: anyext_regclass_sgpr_s1_to_sgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: $sgpr0 = COPY [[COPY]]
+ ; GCN-NEXT: $sgpr0 = COPY [[COPY]]
%0:sgpr(s32) = COPY $sgpr0
%1:sreg_32(s1) = G_TRUNC %0
%2:sgpr(s32) = G_ANYEXT %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
index d642dc0ce612..ef7be3f7cd4a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
@@ -12,8 +12,8 @@ body: |
; GCN-LABEL: name: sext_sgpr_s1_to_sgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: [[S_BFE_I32_:%[0-9]+]]:sreg_32 = S_BFE_I32 [[COPY]], 65536, implicit-def $scc
- ; GCN: $sgpr0 = COPY [[S_BFE_I32_]]
+ ; GCN-NEXT: [[S_BFE_I32_:%[0-9]+]]:sreg_32 = S_BFE_I32 [[COPY]], 65536, implicit-def $scc
+ ; GCN-NEXT: $sgpr0 = COPY [[S_BFE_I32_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s1) = G_TRUNC %0
%2:sgpr(s32) = G_SEXT %1
@@ -31,10 +31,10 @@ body: |
; GCN-LABEL: name: sext_sgpr_s1_to_sgpr_s64
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
- ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
- ; GCN: [[S_BFE_I64_:%[0-9]+]]:sreg_64 = S_BFE_I64 [[REG_SEQUENCE]], 65536, implicit-def $scc
- ; GCN: $sgpr0_sgpr1 = COPY [[S_BFE_I64_]]
+ ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
+ ; GCN-NEXT: [[S_BFE_I64_:%[0-9]+]]:sreg_64 = S_BFE_I64 [[REG_SEQUENCE]], 65536, implicit-def $scc
+ ; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_BFE_I64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s1) = G_TRUNC %0
%2:sgpr(s64) = G_SEXT %1
@@ -52,8 +52,8 @@ body: |
; GCN-LABEL: name: sext_sgpr_s16_to_sgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: [[S_SEXT_I32_I16_:%[0-9]+]]:sreg_32 = S_SEXT_I32_I16 [[COPY]]
- ; GCN: $sgpr0 = COPY [[S_SEXT_I32_I16_]]
+ ; GCN-NEXT: [[S_SEXT_I32_I16_:%[0-9]+]]:sreg_32 = S_SEXT_I32_I16 [[COPY]]
+ ; GCN-NEXT: $sgpr0 = COPY [[S_SEXT_I32_I16_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0
%2:sgpr(s32) = G_SEXT %1
@@ -72,10 +72,10 @@ body: |
; GCN-LABEL: name: sext_sgpr_s16_to_sgpr_s64
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
- ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
- ; GCN: [[S_BFE_I64_:%[0-9]+]]:sreg_64 = S_BFE_I64 [[REG_SEQUENCE]], 1048576, implicit-def $scc
- ; GCN: $sgpr0_sgpr1 = COPY [[S_BFE_I64_]]
+ ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
+ ; GCN-NEXT: [[S_BFE_I64_:%[0-9]+]]:sreg_64 = S_BFE_I64 [[REG_SEQUENCE]], 1048576, implicit-def $scc
+ ; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_BFE_I64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0
%2:sgpr(s64) = G_SEXT %1
@@ -109,8 +109,8 @@ body: |
; GCN-LABEL: name: sext_vgpr_s1_to_vgpr_s32
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GCN: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[COPY]], 0, 1, implicit $exec
- ; GCN: $vgpr0 = COPY [[V_BFE_I32_e64_]]
+ ; GCN-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[COPY]], 0, 1, implicit $exec
+ ; GCN-NEXT: $vgpr0 = COPY [[V_BFE_I32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s1) = G_TRUNC %0
%2:vgpr(s32) = G_SEXT %1
@@ -128,8 +128,8 @@ body: |
; GCN-LABEL: name: sext_vgpr_s16_to_vgpr_s32
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GCN: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[COPY]], 0, 16, implicit $exec
- ; GCN: $vgpr0 = COPY [[V_BFE_I32_e64_]]
+ ; GCN-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[COPY]], 0, 16, implicit $exec
+ ; GCN-NEXT: $vgpr0 = COPY [[V_BFE_I32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s32) = G_SEXT %1
@@ -148,8 +148,8 @@ body: |
; GCN-LABEL: name: sext_sgpr_reg_class_s1_to_sgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: [[S_BFE_I32_:%[0-9]+]]:sreg_32 = S_BFE_I32 [[COPY]], 65536, implicit-def $scc
- ; GCN: $sgpr0 = COPY [[S_BFE_I32_]]
+ ; GCN-NEXT: [[S_BFE_I32_:%[0-9]+]]:sreg_32 = S_BFE_I32 [[COPY]], 65536, implicit-def $scc
+ ; GCN-NEXT: $sgpr0 = COPY [[S_BFE_I32_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sreg_32(s1) = G_TRUNC %0
%2:sgpr(s32) = G_SEXT %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
index 50b3306e92ed..c8d846868976 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
@@ -12,8 +12,8 @@ body: |
; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
- ; GCN: $sgpr0 = COPY [[S_AND_B32_]]
+ ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
+ ; GCN-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s1) = G_TRUNC %0
%2:sgpr(s32) = G_ZEXT %1
@@ -31,10 +31,10 @@ body: |
; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s64
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
- ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
- ; GCN: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 65536, implicit-def $scc
- ; GCN: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
+ ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
+ ; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 65536, implicit-def $scc
+ ; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s1) = G_TRUNC %0
%2:sgpr(s64) = G_ZEXT %1
@@ -52,8 +52,8 @@ body: |
; GCN-LABEL: name: zext_sgpr_s16_to_sgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: [[S_BFE_U32_:%[0-9]+]]:sreg_32 = S_BFE_U32 [[COPY]], 1048576, implicit-def $scc
- ; GCN: $sgpr0 = COPY [[S_BFE_U32_]]
+ ; GCN-NEXT: [[S_BFE_U32_:%[0-9]+]]:sreg_32 = S_BFE_U32 [[COPY]], 1048576, implicit-def $scc
+ ; GCN-NEXT: $sgpr0 = COPY [[S_BFE_U32_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0
%2:sgpr(s32) = G_ZEXT %1
@@ -72,10 +72,10 @@ body: |
; GCN-LABEL: name: zext_sgpr_s16_to_sgpr_s64
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
- ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
- ; GCN: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 1048576, implicit-def $scc
- ; GCN: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
+ ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
+ ; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 1048576, implicit-def $scc
+ ; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0
%2:sgpr(s64) = G_ZEXT %1
@@ -109,8 +109,8 @@ body: |
; GCN-LABEL: name: zext_vgpr_s1_to_vgpr_s32
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GCN: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
- ; GCN: $vgpr0 = COPY [[V_AND_B32_e32_]]
+ ; GCN-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
+ ; GCN-NEXT: $vgpr0 = COPY [[V_AND_B32_e32_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s1) = G_TRUNC %0
%2:vgpr(s32) = G_ZEXT %1
@@ -128,8 +128,8 @@ body: |
; GCN-LABEL: name: zext_vgpr_s16_to_vgpr_s32
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GCN: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[COPY]], 0, 16, implicit $exec
- ; GCN: $vgpr0 = COPY [[V_BFE_U32_e64_]]
+ ; GCN-NEXT: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[COPY]], 0, 16, implicit $exec
+ ; GCN-NEXT: $vgpr0 = COPY [[V_BFE_U32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s32) = G_ZEXT %1
@@ -148,8 +148,8 @@ body: |
; GCN-LABEL: name: zext_sgpr_reg_class_s1_to_sgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
- ; GCN: $sgpr0 = COPY [[S_AND_B32_]]
+ ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
+ ; GCN-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sreg_32(s1) = G_TRUNC %0
%2:sgpr(s32) = G_ZEXT %1
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