[PATCH] D116915: [DAGCombiner][AArch64] Enhance to support for scalar CSINC

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Thanks for the updates - a couple of last comments.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14630
+
+  if (!CSel.hasOneUse() || !RHS.hasOneUse())
+    return SDValue();
----------------
I don't think it matters if the RHS has more than 1 use, it should still be OK to transform as we only use the value in another expression.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14633-14636
+  SDValue CCVal = CSel.getOperand(2);
+  ConstantSDNode *CC = cast<ConstantSDNode>(CCVal);
+  AArch64CC::CondCode AArch64CC =
+      static_cast<AArch64CC::CondCode>(CC->getZExtValue());
----------------
AArch64CC::CondCode AArch64CC = static_cast<AArch64CC::CondCode>(CSel.getConstantOperandVal(2));


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116915/new/

https://reviews.llvm.org/D116915