[PATCH] D118020: [RISCV] Set CostPerUse for floating point registers

[Wang Pengcheng via Phabricator via llvm-commits]

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Set CostPerUse to 1 for floating point registers when RVC is
enabled so that more compressed instructions will be generated.

Code size and performance have some improvements.

SPEC FP 2006 (On Allwinner's D1 <https://reviews.llvm.org/D1> chip, with XuanTie C906):

                   Code size     Performance
  453.povray        -1.145%        +7.926%
  433.milc             -           +1.399%
  450.soplex        -0.905%        +1.177%
  470.lbm              -           +0.188%
  444.namd          -1.882%        +0.124%
  447.dealII        -0.440%        +0.053%
  482.sphinx3          -           -1.569%

For CSiBE, we reduced 1%-5% code size under `-Oz`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D118020

Files:
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

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