[PATCH] D114642: [AArch64][SchedModels] Handle virtual registers in FP/NEON predicates

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

This gets used by the exynos cpu schedule models, which are something I know little about. Ideally someone from that team would be able to check this and verify it was OK for performance. I'm not sure if that team exists in the same form it did in the past though.



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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.h:106
 
+  /// Returns whether the instruction is FP or NEON.
+  static bool isFpOrNEON(const MachineInstr &MI);
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This isn't a very general function if it only checks operand 0. There are AArch64 instructions that I would count as FP that return in X/W registers (the fcvt's for example). Perhaps make it clean in the description, that it is designed for use in scheduling models and only checks operand 0.

I would move this to bellow the getLoadStoreImmIdx and isPairableLdStInst too, so that the "load/store" functions can be kept together.


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Comment at: llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir:40
+    %1:fpr128 = COPY $q1
+    %2:fpr128 = COPY %1
+    $q0 = COPY %2
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Is it possible to a better example? COPY instructions (especially no-op copys like these) are often expected to be removed by reg-alloc and any scheduling info you give them is likely misleading.


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https://reviews.llvm.org/D114642