[llvm] f533011 - [Hexagon] Use llvm::Register instead of unsigned in HexagonConstExtenders.cpp. NFC.

[Jim Lin via llvm-commits]

Author: Jim Lin
Date: 2022-01-24T16:06:25+08:00
New Revision: f533011252578f67a9615fb4ef56dc1ef555551b

URL: https://github.com/llvm/llvm-project/commit/f533011252578f67a9615fb4ef56dc1ef555551b
DIFF: https://github.com/llvm/llvm-project/commit/f533011252578f67a9615fb4ef56dc1ef555551b.diff

LOG: [Hexagon] Use llvm::Register instead of unsigned in HexagonConstExtenders.cpp. NFC.

Reviewed By: kparzysz

Differential Revision: https://reviews.llvm.org/D117851

Added: 
    

Modified: 
    llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
index d3fcdb6ae9a85..d8af35cbf3a89 100644
--- a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
@@ -229,7 +229,7 @@ namespace {
   private:
     struct Register {
       Register() = default;
-      Register(unsigned R, unsigned S) : Reg(R), Sub(S) {}
+      Register(llvm::Register R, unsigned S) : Reg(R), Sub(S) {}
       Register(const MachineOperand &Op)
         : Reg(Op.getReg()), Sub(Op.getSubReg()) {}
       Register &operator=(const MachineOperand &Op) {
@@ -1573,7 +1573,7 @@ HCE::Register HCE::insertInitializer(Loc DefL, const ExtenderInit &ExtI) {
         // No compounds are available. It is not clear whether we should
         // even process such extenders where the initializer cannot be
         // a single instruction, but do it for now.
-        unsigned TmpR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
+        llvm::Register TmpR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
         BuildMI(MBB, At, dl, HII->get(Hexagon::S2_asl_i_r), TmpR)
           .add(MachineOperand(Ex.Rs))
           .addImm(Ex.S);