[PATCH] D117920: [RISCV] Decouple V and Zve64*

[Yueh-Ting Chen via Phabricator via llvm-commits]

eopXD updated this revision to Diff 402085.
eopXD added a comment.

Update code.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117920/new/

https://reviews.llvm.org/D117920

Files:
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===================================================================
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -732,7 +732,7 @@
   return Error::success();
 }
 
-static const char *ImpliedExtsV[] = {"zvl128b", "zve64d", "f", "d"};
+static const char *ImpliedExtsV[] = {"zvl128b", "zve32x", "f", "d"};
 static const char *ImpliedExtsZfh[] = {"zfhmin"};
 static const char *ImpliedExtsZve64d[] = {"zve64f"};
 static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
@@ -844,6 +844,9 @@
   // handles EEW restriction by sub-extension zve
   for (auto Ext : Exts) {
     StringRef ExtName = Ext.first;
+    if (ExtName == "v") {
+      MaxELen = MaxELenFp = 64;
+    }
     bool IsZveExt = ExtName.consume_front("zve");
     if (IsZveExt) {
       if (ExtName.back() == 'f')


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