[llvm] 48132bb - [RISCV] Simplify interface to combineMUL_VLToVWMUL. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 21 11:43:27 PST 2022
Author: Craig Topper
Date: 2022-01-21T11:43:06-08:00
New Revision: 48132bb1e437f213e7a183a6a69e7589abe33af6
URL: https://github.com/llvm/llvm-project/commit/48132bb1e437f213e7a183a6a69e7589abe33af6
DIFF: https://github.com/llvm/llvm-project/commit/48132bb1e437f213e7a183a6a69e7589abe33af6.diff
LOG: [RISCV] Simplify interface to combineMUL_VLToVWMUL. NFC
Instead of passing the both the SDNode* and 2 of the operands
in two different orders, just pass the SDNode * and a bool to
indicate which operand order to test.
While there rename to combineMUL_VLToVWMUL_VL.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 4aba42b014d1..e1f1c4909442 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -7242,9 +7242,14 @@ static SDValue performANY_EXTENDCombine(SDNode *N,
// Try to form VWMUL or VWMULU.
// FIXME: Support VWMULSU.
-static SDValue combineMUL_VLToVWMUL(SDNode *N, SDValue Op0, SDValue Op1,
- SelectionDAG &DAG) {
+static SDValue combineMUL_VLToVWMUL_VL(SDNode *N, SelectionDAG &DAG,
+ bool Commute) {
assert(N->getOpcode() == RISCVISD::MUL_VL && "Unexpected opcode");
+ SDValue Op0 = N->getOperand(0);
+ SDValue Op1 = N->getOperand(1);
+ if (Commute)
+ std::swap(Op0, Op1);
+
bool IsSignExt = Op0.getOpcode() == RISCVISD::VSEXT_VL;
bool IsZeroExt = Op0.getOpcode() == RISCVISD::VZEXT_VL;
if ((!IsSignExt && !IsZeroExt) || !Op0.hasOneUse())
@@ -7887,15 +7892,11 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
}
break;
}
- case RISCVISD::MUL_VL: {
- SDValue Op0 = N->getOperand(0);
- SDValue Op1 = N->getOperand(1);
- if (SDValue V = combineMUL_VLToVWMUL(N, Op0, Op1, DAG))
+ case RISCVISD::MUL_VL:
+ if (SDValue V = combineMUL_VLToVWMUL_VL(N, DAG, /*Commute*/ false))
return V;
- if (SDValue V = combineMUL_VLToVWMUL(N, Op1, Op0, DAG))
- return V;
- return SDValue();
- }
+ // Mul is commutative.
+ return combineMUL_VLToVWMUL_VL(N, DAG, /*Commute*/ true);
case ISD::STORE: {
auto *Store = cast<StoreSDNode>(N);
SDValue Val = Store->getValue();
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