[PATCH] D112326: [AArch64] Async unwind - do not schedule frame setup/destroy

[Momchil Velikov via Phabricator via llvm-commits]

chill updated this revision to Diff 402048.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112326/new/

https://reviews.llvm.org/D112326

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/byval-call.ll
  llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-no-helper.ll
  llvm/test/CodeGen/AArch64/framelayout-frame-record.mir
  llvm/test/CodeGen/AArch64/framelayout-unaligned-fp.ll


Index: llvm/test/CodeGen/AArch64/framelayout-unaligned-fp.ll
===================================================================
--- llvm/test/CodeGen/AArch64/framelayout-unaligned-fp.ll
+++ llvm/test/CodeGen/AArch64/framelayout-unaligned-fp.ll
@@ -28,8 +28,8 @@
 ; CHECK-LABEL: b:
 ; CHECK:       str     d8, [sp, #-32]!
 ; CHECK-NEXT:  stp     x29, x30, [sp, #8]
-; CHECK-NEXT:  add     x29, sp, #8
 ; CHECK-NEXT:  str     x19, [sp, #24]
+; CHECK-NEXT:  add     x29, sp, #8
 
 ; CHECK:       sub     sp, x29, #8
 ; CHECK-NEXT:  ldp     x29, x30, [sp, #8]
Index: llvm/test/CodeGen/AArch64/framelayout-frame-record.mir
===================================================================
--- llvm/test/CodeGen/AArch64/framelayout-frame-record.mir
+++ llvm/test/CodeGen/AArch64/framelayout-frame-record.mir
@@ -16,8 +16,8 @@
 
 # CHECK: stp d9, d8, [sp, #-48]!
 # CHECK: stp x29, x30, [sp, #16]
-# CHECK: add x29, sp, #16
 # CHECK: str x19, [sp, #32]
+# CHECK: add x29, sp, #16
 
 # CHECK: .cfi_def_cfa w29, 32
 # CHECK: .cfi_offset w19, -16
Index: llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-no-helper.ll
===================================================================
--- llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-no-helper.ll
+++ llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-no-helper.ll
@@ -47,8 +47,8 @@
 ; CHECK-LINUX-NEXT:    stp d11, d10, [sp, #-64]!
 ; CHECK-LINUX-NEXT:    stp d9, d8, [sp, #16]
 ; CHECK-LINUX-NEXT:    stp x29, x30, [sp, #32]
-; CHECK-LINUX-NEXT:    add x29, sp, #32
 ; CHECK-LINUX-NEXT:    stp x20, x19, [sp, #48]
+; CHECK-LINUX-NEXT:    add x29, sp, #32
 ; CHECK-LINUX-NEXT:    .cfi_def_cfa w29, 32
 ; CHECK-LINUX-NEXT:    .cfi_offset w19, -8
 ; CHECK-LINUX-NEXT:    .cfi_offset w20, -16
Index: llvm/test/CodeGen/AArch64/GlobalISel/byval-call.ll
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/byval-call.ll
+++ llvm/test/CodeGen/AArch64/GlobalISel/byval-call.ll
@@ -27,8 +27,8 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #288
 ; CHECK-NEXT:    stp x29, x30, [sp, #256] // 16-byte Folded Spill
-; CHECK-NEXT:    add x29, sp, #256
 ; CHECK-NEXT:    str x28, [sp, #272] // 8-byte Folded Spill
+; CHECK-NEXT:    add x29, sp, #256
 ; CHECK-NEXT:    .cfi_def_cfa w29, 32
 ; CHECK-NEXT:    .cfi_offset w28, -16
 ; CHECK-NEXT:    .cfi_offset w30, -24
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -1105,7 +1105,10 @@
     return true;
   default:;
   }
-  return isSEHInstruction(MI);
+  if (isSEHInstruction(MI))
+    return true;
+  auto Next = std::next(MI.getIterator());
+  return Next != MBB->end() && Next->isCFIInstruction();
 }
 
 /// analyzeCompare - For a comparison instruction, return the source registers


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