[PATCH] D116821: [DebugInfo][InstrRef] Move instr-ref controlling flag out of TargetOptions

[Alexandre Ganea via Phabricator via llvm-commits]

aganea added a comment.

In D116821#3261205 <https://reviews.llvm.org/D116821#3261205>, @mstorsjo wrote:

> In D116821#3261109 <https://reviews.llvm.org/D116821#3261109>, @mstorsjo wrote:
>
>> I ran into a regression with this patch, which triggers the error "fatal error: error in backend: unknown codeview register ST0" on code that built fine before that.
>>
>> Here's a reduced reproducer:
>>
>>   $ cat dither.c 
>>   a() {
>>     long double b;
>>     asm volatile("" : "=t"(b));
>>   }
>>   $ clang -target x86_64-w64-mingw32 -c -O2 -g -gcodeview dither.c 
>>   fatal error: error in backend: unknown codeview register ST0
>>   PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace, preprocessed source, and associated run script.
>>   Stack dump:
>>   0.	Program arguments: bin/clang -target x86_64-w64-mingw32 -c -O2 -g -gcodeview dither.c
>>   1.	<eof> parser at end of file
>>   2.	Code generation
>>   3.	Running pass 'Function Pass Manager' on module 'dither.c'.
>>   4.	Running pass 'X86 Assembly Printer' on function '@a'
>
> Do @rnk or @aganea have any clue about this?

Some mappings seem to be missing, but I don't know why the `Location->Register` didn't return the FPU stack ST0-ST7 before? Here: https://github.com/llvm/llvm-project/blob/main/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp#L1348

  diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
  index 9da0a8129f23..c83c211b0c58 100644
  --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
  +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
  @@ -111,6 +111,15 @@ void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) {
  
         {codeview::RegisterId::EFLAGS, X86::EFLAGS},
  
  +      {codeview::RegisterId::ST0, X86::ST0},
  +      {codeview::RegisterId::ST1, X86::ST1},
  +      {codeview::RegisterId::ST2, X86::ST2},
  +      {codeview::RegisterId::ST3, X86::ST3},
  +      {codeview::RegisterId::ST4, X86::ST4},
  +      {codeview::RegisterId::ST5, X86::ST5},
  +      {codeview::RegisterId::ST6, X86::ST6},
  +      {codeview::RegisterId::ST7, X86::ST7},
  +
         {codeview::RegisterId::ST0, X86::FP0},
         {codeview::RegisterId::ST1, X86::FP1},
         {codeview::RegisterId::ST2, X86::FP2},


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