[PATCH] D117871: [AArch64][CodeGen] Always use SVE (when enabled) to lower integer divides

[David Sherwood via Phabricator via llvm-commits]

david-arm created this revision.
david-arm added reviewers: sdesmalen, bsmith, paulwalker-arm, kmclaughlin, peterwaller-arm.
Herald added subscribers: ctetreau, hiraditya, kristof.beyls, tschuett.
david-arm requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

This patch adds customer lowering support for ISD::SDIV and ISD::UDIV
when SVE is enabled, regardless of the minimum SVE vector length. We do
this because NEON simply does not have vector integer divide support, so
we want to take advantage of these instructions in SVE. Doing this
required changing the interfaces a little to get more fine-tuned control
of when we want to use SVE instructions for NEON-sized (64 and 128 bit)
vectors. To this effect, I've added a new enum class called NeonOverride
that has three values:

1. 'Never' - never override NEON-sized vectors to use SVE.
2. 'OnlyIfSVEGreaterThan128Bits' - only override if the min SVE vector

length > 128 bits.

3. 'Always' - does what it says on the tin!

Now useSVEForFixedLengthVectorVT takes this new enum as a parameter
instead of the existing OverrideNEON boolean, and when lowering
vector integer divides we pass in the Always option.

As part of this patch I've also simplified LowerToPredicatedOp to avoid
re-asking the same question about whether we should be using SVE for
fixed length vectors. Once we've made the decision to call
LowerToPredicatedOp, then we should simply assert we should be using SVE.

I've pulled the 128-bit min SVE vector bits tests out of

  CodeGen/AArch64/sve-fixed-length-int-div.ll
  CodeGen/AArch64/sve-fixed-length-int-rem.ll

and moved them here instead

  CodeGen/AArch64/sve-fixed-length-int-div-128.ll
  CodeGen/AArch64/sve-fixed-length-int-rem-128.ll


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117871

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-div-128.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem-128.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll

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