[PATCH] D117854: [RISCV] Refactor Zve* extensions.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added a comment.

In D117854#3260392 <https://reviews.llvm.org/D117854#3260392>, @eopXD wrote:

> I see your point now.
>
> In the v-spec describing for `Zve`:
>
>> All Zve* extensions support all vector integer instructions (Section Vector Integer Arithmetic Instructions), except that the vmulh integer multiply variants that return the high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*.
>
> For V extension:
>
>> The V extension supports all vector integer instructions (Section Vector Integer Arithmetic Instructions).
>
> So we need to have something to express that V is enabled.
>
> ------
>
> If I have parsed correctly in the above, I think we should have something that indicates V ext. is specified rather than adding `HasStdExtV` to the existing predicates.

In my opinion, `FeatureStdExtV` just means that we have the V extension. In the instruction level, the V extension includes all the Zve* extensions. But they still have different using space which V is for application processors and Zve* is for embedded processors. Maybe it's better to not mix these two things?


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