[PATCH] D117854: [RISCV] Refactor Zve* extensions.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added a comment.

In D117854#3260368 <https://reviews.llvm.org/D117854#3260368>, @eopXD wrote:

> FeatureStdExtV will imply Zve32x, Zve64x, Zve32f and Zve64d, both `RISCV.td` or `RISCVISAInfo` does so.
> So I wonder why do we need the extra condition here.
> May you tell more?

For example, if I want to make vmulhsu.vv disable for Zve64d when EEW=64, I need some predicates or condition asserts to make sure that current target just implement only Zve64d but not the V extension.


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https://reviews.llvm.org/D117854