[PATCH] D117854: [RISCV] Refactor Zve* extensions.

[Yueh-Ting Chen via Phabricator via llvm-commits]

eopXD added a comment.

FeatureStdExtV will imply Zve32x, Zve64x, Zve32f and Zve64d, both `RISCV.td` or `RISCVISAInfo` does so.
So I wonder why do we need the extra condition here.
May you tell more?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D117854/new/

https://reviews.llvm.org/D117854