[llvm] 7ee1c16 - [RISCV][RFC] add inst support of zbkb
Wu Xinlong via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 20 19:49:45 PST 2022
Author: Wu Xinlong
Date: 2022-01-21T11:49:36+08:00
New Revision: 7ee1c162cc53d37f717f9a138276ad64fa6863bc
URL: https://github.com/llvm/llvm-project/commit/7ee1c162cc53d37f717f9a138276ad64fa6863bc
DIFF: https://github.com/llvm/llvm-project/commit/7ee1c162cc53d37f717f9a138276ad64fa6863bc.diff
LOG: [RISCV][RFC] add inst support of zbkb
This commit add instructions supports of `zbkb` which defined in scalar cryptography extension version v1.0.0 (has been ratified already).
Most of the zbkb directives reuse parts of the zbp and zbb directives, so this patch just modified some of the inst aliases and predicates.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D117640
Added:
llvm/test/MC/RISCV/rv32zbkb-only-valid.s
llvm/test/MC/RISCV/rv32zbkb-valid.s
llvm/test/MC/RISCV/rv64-zbkb-valid.s
llvm/test/MC/RISCV/rv64zbkb-only-valid.s
Modified:
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
llvm/lib/Target/RISCV/RISCVSchedRocket.td
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/CodeGen/RISCV/rv32zbp.ll
llvm/test/CodeGen/RISCV/rv64zbp.ll
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/rv32zbp-aliases-valid.s
llvm/test/MC/RISCV/rv32zbp-only-valid.s
llvm/test/MC/RISCV/rv32zbp-valid.s
llvm/test/MC/RISCV/rv64zbp-aliases-valid.s
Removed:
################################################################################
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index fc52fc6803439..0d9b6e4fa4bb5 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -55,6 +55,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"zbb", RISCVExtensionVersion{1, 0}},
{"zbc", RISCVExtensionVersion{1, 0}},
{"zbs", RISCVExtensionVersion{1, 0}},
+
+ {"zbkb", RISCVExtensionVersion{1, 0}},
};
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index b5d2bd01d3552..378720bc6b26d 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -143,6 +143,26 @@ def HasStdExtZbbOrZbp
"'Zbb' (Base 'B' Instructions) or "
"'Zbp' (Permutation 'B' Instructions)">;
+def FeatureStdExtZbkb
+ : SubtargetFeature<"zbkb", "HasStdExtZbkb", "true",
+ "'Zbkb' (Bitmanip instructions for Cryptography)">;
+def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
+ AssemblerPredicate<(all_of FeatureStdExtZbkb),
+ "'Zbkb' (Bitmanip instructions for Cryptography)">;
+
+def HasStdExtZbpOrZbkb
+ : Predicate<"Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkb()">,
+ AssemblerPredicate<(any_of FeatureStdExtZbp, FeatureStdExtZbkb),
+ "'Zbp' (Permutation 'B' Instructions) or "
+ "'Zbkb' (Bitmanip instructions for Cryptography)">;
+
+def HasStdExtZbbOrZbpOrZbkb
+ : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkb()">,
+ AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbp, FeatureStdExtZbkb),
+ "'Zbb' (Base 'B' Instructions) or "
+ "'Zbp' (Permutation 'B' Instructions) or "
+ "'Zbkb' (Bitmanip instructions for Cryptography)">;
+
def FeatureNoRVCHints
: SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
"Disable RVC Hint Instructions.">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index f23fd2adb665b..f8030b35da3a2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -313,14 +313,14 @@ class RVBTernaryImm5<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode,
// Instructions
//===----------------------------------------------------------------------===//
-let Predicates = [HasStdExtZbbOrZbp] in {
+let Predicates = [HasStdExtZbbOrZbpOrZbkb] in {
def ANDN : ALU_rr<0b0100000, 0b111, "andn">,
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
def ORN : ALU_rr<0b0100000, 0b110, "orn">,
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
def XNOR : ALU_rr<0b0100000, 0b100, "xnor">,
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
-} // Predicates = [HasStdExtZbbOrZbp]
+} // Predicates = [HasStdExtZbbOrZbpOrZbkb]
let Predicates = [HasStdExtZba] in {
def SH1ADD : ALU_rr<0b0010000, 0b010, "sh1add">,
@@ -331,12 +331,12 @@ def SH3ADD : ALU_rr<0b0010000, 0b110, "sh3add">,
Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
} // Predicates = [HasStdExtZba]
-let Predicates = [HasStdExtZbbOrZbp] in {
+let Predicates = [HasStdExtZbbOrZbpOrZbkb] in {
def ROL : ALU_rr<0b0110000, 0b001, "rol">,
Sched<[WriteRotateReg, ReadRotateReg, ReadRotateReg]>;
def ROR : ALU_rr<0b0110000, 0b101, "ror">,
Sched<[WriteRotateReg, ReadRotateReg, ReadRotateReg]>;
-} // Predicates = [HasStdExtZbbOrZbp]
+} // Predicates = [HasStdExtZbbOrZbpOrZbkb]
let Predicates = [HasStdExtZbs] in {
def BCLR : ALU_rr<0b0100100, 0b001, "bclr">,
@@ -360,7 +360,7 @@ def XPERMB : ALU_rr<0b0010100, 0b100, "xperm.b">, Sched<[]>;
def XPERMH : ALU_rr<0b0010100, 0b110, "xperm.h">, Sched<[]>;
} // Predicates = [HasStdExtZbp]
-let Predicates = [HasStdExtZbbOrZbp] in
+let Predicates = [HasStdExtZbbOrZbpOrZbkb] in
def RORI : RVBShift_ri<0b01100, 0b101, OPC_OP_IMM, "rori">,
Sched<[WriteRotateImm, ReadRotateImm]>;
@@ -471,11 +471,13 @@ def BDECOMPRESS : ALU_rr<0b0100100, 0b110, "bdecompress">, Sched<[]>;
def BCOMPRESS : ALU_rr<0b0000100, 0b110, "bcompress">, Sched<[]>;
} // Predicates = [HasStdExtZbe]
-let Predicates = [HasStdExtZbp] in {
+let Predicates = [HasStdExtZbpOrZbkb] in {
def PACK : ALU_rr<0b0000100, 0b100, "pack">, Sched<[]>;
-def PACKU : ALU_rr<0b0100100, 0b100, "packu">, Sched<[]>;
def PACKH : ALU_rr<0b0000100, 0b111, "packh">, Sched<[]>;
-} // Predicates = [HasStdExtZbp]
+} // Predicates = [HasStdExtZbpOrZbkb]
+
+let Predicates = [HasStdExtZbp] in
+def PACKU : ALU_rr<0b0100100, 0b100, "packu">, Sched<[]>;
let Predicates = [HasStdExtZbm, IsRV64] in {
def BMATOR : ALU_rr<0b0000100, 0b011, "bmator">, Sched<[]>;
@@ -504,7 +506,7 @@ def SH3ADDUW : ALUW_rr<0b0010000, 0b110, "sh3add.uw">,
Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
} // Predicates = [HasStdExtZbb, IsRV64]
-let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
+let Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64] in {
def ROLW : ALUW_rr<0b0110000, 0b001, "rolw">,
Sched<[WriteRotateReg32, ReadRotateReg32, ReadRotateReg32]>;
def RORW : ALUW_rr<0b0110000, 0b101, "rorw">,
@@ -520,7 +522,7 @@ let Predicates = [HasStdExtZbp, IsRV64] in {
def XPERMW : ALU_rr<0b0010100, 0b000, "xperm.w">, Sched<[]>;
} // Predicates = [HasStdExtZbp, IsRV64]
-let Predicates = [HasStdExtZbbOrZbp, IsRV64] in
+let Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64] in
def RORIW : RVBShiftW_ri<0b0110000, 0b101, OPC_OP_IMM_32, "roriw">,
Sched<[WriteRotateImm32, ReadRotateImm32]>;
@@ -559,10 +561,11 @@ def BDECOMPRESSW : ALUW_rr<0b0100100, 0b110, "bdecompressw">, Sched<[]>;
def BCOMPRESSW : ALUW_rr<0b0000100, 0b110, "bcompressw">, Sched<[]>;
} // Predicates = [HasStdExtZbe, IsRV64]
-let Predicates = [HasStdExtZbp, IsRV64] in {
+let Predicates = [HasStdExtZbpOrZbkb, IsRV64] in
def PACKW : ALUW_rr<0b0000100, 0b100, "packw">, Sched<[]>;
+
+let Predicates = [HasStdExtZbp, IsRV64] in
def PACKUW : ALUW_rr<0b0100100, 0b100, "packuw">, Sched<[]>;
-} // Predicates = [HasStdExtZbp, IsRV64]
let Predicates = [HasStdExtZbf, IsRV64] in
def BFPW : ALUW_rr<0b0100100, 0b111, "bfpw">,
@@ -593,21 +596,21 @@ def ZEXTH_RV64 : RVInstR<0b0000100, 0b100, OPC_OP_32, (outs GPR:$rd),
// causes diagnostics to suggest that Zbp rather than Zbb is required for rev8
// or gorci. Since Zbb is closer to being finalized than Zbp this will be
// misleading to users.
-let Predicates = [HasStdExtZbbOrZbp, IsRV32] in {
+let Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV32] in {
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
def REV8_RV32 : RVInstI<0b101, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
"rev8", "$rd, $rs1">, Sched<[WriteREV8, ReadREV8]> {
let imm12 = { 0b01101, 0b0011000 };
}
-} // Predicates = [HasStdExtZbbOrZbp, IsRV32]
+} // Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV32]
-let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
+let Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64] in {
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
def REV8_RV64 : RVInstI<0b101, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
"rev8", "$rd, $rs1">, Sched<[WriteREV8, ReadREV8]> {
let imm12 = { 0b01101, 0b0111000 };
}
-} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
+} // Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64]
let Predicates = [HasStdExtZbbOrZbp] in {
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
@@ -617,6 +620,15 @@ def ORCB : RVInstI<0b101, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
}
} // Predicates = [HasStdExtZbbOrZbp]
+let Predicates = [HasStdExtZbpOrZbkb] in
+def BREV8 : RVBUnary<0b0110100, 0b00111, 0b101, OPC_OP_IMM, "brev8">;
+
+let Predicates = [HasStdExtZbpOrZbkb, IsRV32] in {
+def ZIP_RV32 : RVBUnary<0b0000100, 0b01111, 0b001, OPC_OP_IMM, "zip">;
+def UNZIP_RV32 : RVBUnary<0b0000100, 0b01111, 0b101, OPC_OP_IMM, "unzip">;
+} // Predicates = [HasStdExtZbkb, IsRV32]
+
+
//===----------------------------------------------------------------------===//
// Pseudo Instructions
//===----------------------------------------------------------------------===//
@@ -631,11 +643,11 @@ def : InstAlias<"rev2.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00010)>;
def : InstAlias<"rev.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00011)>;
def : InstAlias<"rev4.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00100)>;
def : InstAlias<"rev2.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00110)>;
-def : InstAlias<"rev.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00111)>;
def : InstAlias<"rev8.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01000)>;
def : InstAlias<"rev4.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01100)>;
def : InstAlias<"rev2.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01110)>;
def : InstAlias<"rev.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01111)>;
+def : InstAlias<"rev.b $rd, $rs", (BREV8 GPR:$rd, GPR:$rs)>;
def : InstAlias<"zip.n $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0001)>;
def : InstAlias<"unzip.n $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0001)>;
@@ -675,8 +687,6 @@ def : InstAlias<"zip4 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1100)>;
def : InstAlias<"unzip4 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1100)>;
def : InstAlias<"zip2 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1110)>;
def : InstAlias<"unzip2 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1110)>;
-def : InstAlias<"zip $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1111)>;
-def : InstAlias<"unzip $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1111)>;
def : InstAlias<"orc16 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b10000)>;
def : InstAlias<"orc8 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11000)>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
index b907ada3a1d5a..6cc24fa17c84a 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
@@ -17,7 +17,7 @@ def RocketModel : SchedMachineModel {
let LoadLatency = 3;
let MispredictPenalty = 3;
let CompleteModel = false;
- let UnsupportedFeatures = [HasVInstructions, HasVInstructionsI64];
+ let UnsupportedFeatures = [HasStdExtZbkb, HasVInstructions, HasVInstructionsI64];
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 5672637a40cc2..2da8c14088890 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -15,7 +15,7 @@ def SiFive7Model : SchedMachineModel {
let LoadLatency = 3;
let MispredictPenalty = 3;
let CompleteModel = 0;
- let UnsupportedFeatures = [HasVInstructions];
+ let UnsupportedFeatures = [HasStdExtZbkb, HasVInstructions];
}
// The SiFive7 microarchitecture has two pipelines: A and B.
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 4b5958ad38d9c..141e7114b5883 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -83,6 +83,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool HasStdExtZve64d = false;
bool HasStdExtZfhmin = false;
bool HasStdExtZfh = false;
+ bool HasStdExtZbkb = false;
bool HasRV64 = false;
bool IsRV32E = false;
bool EnableLinkerRelax = false;
@@ -156,6 +157,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool hasStdExtZvl() const { return ZvlLen != ExtZvl::NotSet; }
bool hasStdExtZfhmin() const { return HasStdExtZfhmin; }
bool hasStdExtZfh() const { return HasStdExtZfh; }
+ bool hasStdExtZbkb() const { return HasStdExtZbkb; }
bool is64Bit() const { return HasRV64; }
bool isRV32E() const { return IsRV32E; }
bool enableLinkerRelax() const { return EnableLinkerRelax; }
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 59790c9967111..dd4a340edeac4 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -19,6 +19,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v %s -o - | FileCheck --check-prefix=RV32V %s
; RUN: llc -mtriple=riscv32 -mattr=+zbb,+zfh,+experimental-v,+f %s -o - | FileCheck --check-prefix=RV32COMBINED %s
+; RUN: llc -mtriple=riscv32 -mattr=+zbkb %s -o - | FileCheck --check-prefix=RV32ZBKB %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
@@ -38,6 +39,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v %s -o - | FileCheck --check-prefix=RV64V %s
; RUN: llc -mtriple=riscv64 -mattr=+zbb,+zfh,+experimental-v,+f %s -o - | FileCheck --check-prefix=RV64COMBINED %s
+; RUN: llc -mtriple=riscv64 -mattr=+zbkb %s -o - | FileCheck --check-prefix=RV64ZBKB %s
; RV32M: .attribute 5, "rv32i2p0_m2p0"
@@ -59,6 +61,7 @@
; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+; RV32ZBKB: .attribute 5, "rv32i2p0_zbkb1p0"
; RV64M: .attribute 5, "rv64i2p0_m2p0"
; RV64A: .attribute 5, "rv64i2p0_a2p0"
@@ -79,6 +82,7 @@
; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+; RV64ZBKB: .attribute 5, "rv64i2p0_zbkb1p0"
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
diff --git a/llvm/test/CodeGen/RISCV/rv32zbp.ll b/llvm/test/CodeGen/RISCV/rv32zbp.ll
index 026a27b691196..1e2b0322b3688 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbp.ll
@@ -1491,7 +1491,7 @@ define i32 @grev7_i32(i32 %a) nounwind {
;
; RV32ZBP-LABEL: grev7_i32:
; RV32ZBP: # %bb.0:
-; RV32ZBP-NEXT: rev.b a0, a0
+; RV32ZBP-NEXT: grevi a0, a0, 7
; RV32ZBP-NEXT: ret
%and1 = shl i32 %a, 1
%shl1 = and i32 %and1, -1431655766
@@ -1560,8 +1560,8 @@ define i64 @grev7_i64(i64 %a) nounwind {
;
; RV32ZBP-LABEL: grev7_i64:
; RV32ZBP: # %bb.0:
-; RV32ZBP-NEXT: rev.b a0, a0
-; RV32ZBP-NEXT: rev.b a1, a1
+; RV32ZBP-NEXT: grevi a0, a0, 7
+; RV32ZBP-NEXT: grevi a1, a1, 7
; RV32ZBP-NEXT: ret
%and1 = shl i64 %a, 1
%shl1 = and i64 %and1, -6148914691236517206
@@ -2175,7 +2175,7 @@ define zeroext i8 @bitreverse_i8(i8 zeroext %a) nounwind {
;
; RV32ZBP-LABEL: bitreverse_i8:
; RV32ZBP: # %bb.0:
-; RV32ZBP-NEXT: rev.b a0, a0
+; RV32ZBP-NEXT: grevi a0, a0, 7
; RV32ZBP-NEXT: ret
%1 = tail call i8 @llvm.bitreverse.i8(i8 %a)
ret i8 %1
@@ -2450,7 +2450,7 @@ define i32 @bitreverse_bswap_i32(i32 %a) {
;
; RV32ZBP-LABEL: bitreverse_bswap_i32:
; RV32ZBP: # %bb.0:
-; RV32ZBP-NEXT: rev.b a0, a0
+; RV32ZBP-NEXT: grevi a0, a0, 7
; RV32ZBP-NEXT: ret
%1 = call i32 @llvm.bitreverse.i32(i32 %a)
%2 = call i32 @llvm.bswap.i32(i32 %1)
@@ -2539,8 +2539,8 @@ define i64 @bitreverse_bswap_i64(i64 %a) {
;
; RV32ZBP-LABEL: bitreverse_bswap_i64:
; RV32ZBP: # %bb.0:
-; RV32ZBP-NEXT: rev.b a0, a0
-; RV32ZBP-NEXT: rev.b a1, a1
+; RV32ZBP-NEXT: grevi a0, a0, 7
+; RV32ZBP-NEXT: grevi a1, a1, 7
; RV32ZBP-NEXT: ret
%1 = call i64 @llvm.bitreverse.i64(i64 %a)
%2 = call i64 @llvm.bswap.i64(i64 %1)
diff --git a/llvm/test/CodeGen/RISCV/rv64zbp.ll b/llvm/test/CodeGen/RISCV/rv64zbp.ll
index 674ffcff180de..5b74675cdb3ff 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbp.ll
@@ -1438,7 +1438,7 @@ define i64 @grev7_i64(i64 %a) nounwind {
;
; RV64ZBP-LABEL: grev7_i64:
; RV64ZBP: # %bb.0:
-; RV64ZBP-NEXT: rev.b a0, a0
+; RV64ZBP-NEXT: grevi a0, a0, 7
; RV64ZBP-NEXT: ret
%and1 = shl i64 %a, 1
%shl1 = and i64 %and1, -6148914691236517206
@@ -2481,7 +2481,7 @@ define i64 @bitreverse_bswap_i64(i64 %a) {
;
; RV64ZBP-LABEL: bitreverse_bswap_i64:
; RV64ZBP: # %bb.0:
-; RV64ZBP-NEXT: rev.b a0, a0
+; RV64ZBP-NEXT: grevi a0, a0, 7
; RV64ZBP-NEXT: ret
%1 = call i64 @llvm.bitreverse.i64(i64 %a)
%2 = call i64 @llvm.bswap.i64(i64 %1)
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 3d7be42caeb56..703b6a6aa8105 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -127,3 +127,6 @@
.attribute arch, "rv32ifd_zve64d0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl32b0p10_zvl64b0p10"
+
+.attribute arch, "rv32i_zbkb1p0"
+# CHECK: attribute 5, "rv32i2p0_zbkb1p0"
diff --git a/llvm/test/MC/RISCV/rv32zbkb-only-valid.s b/llvm/test/MC/RISCV/rv32zbkb-only-valid.s
new file mode 100644
index 0000000000000..a04ff04ba3f10
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zbkb-only-valid.s
@@ -0,0 +1,16 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zbkb -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zbkb < %s \
+# RUN: | llvm-objdump --mattr=+zbkb -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: rev8 t0, t1
+# CHECK-ASM: encoding: [0x93,0x52,0x83,0x69]
+rev8 t0, t1
+
+# CHECK-ASM-AND-OBJ: zip t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0xf3,0x08]
+zip t0, t1
+# CHECK-S-OBJ-NOALIAS: unzip t0, t1
+# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x08]
+unzip t0, t1
diff --git a/llvm/test/MC/RISCV/rv32zbkb-valid.s b/llvm/test/MC/RISCV/rv32zbkb-valid.s
new file mode 100644
index 0000000000000..36e0a27922776
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zbkb-valid.s
@@ -0,0 +1,45 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zbkb -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbkb -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zbkb < %s \
+# RUN: | llvm-objdump --mattr=+zbkb -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbkb < %s \
+# RUN: | llvm-objdump --mattr=+zbkb -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: ror t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x60]
+ror t0, t1, t2
+# CHECK-ASM-AND-OBJ: rol t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x60]
+rol t0, t1, t2
+# CHECK-ASM-AND-OBJ: rori t0, t1, 31
+# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x61]
+rori t0, t1, 31
+# CHECK-ASM-AND-OBJ: rori t0, t1, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x60]
+rori t0, t1, 0
+
+# CHECK-ASM-AND-OBJ: andn t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x40]
+andn t0, t1, t2
+# CHECK-ASM-AND-OBJ: orn t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x40]
+orn t0, t1, t2
+# CHECK-ASM-AND-OBJ: xnor t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x40]
+xnor t0, t1, t2
+
+# CHECK-ASM: pack t0, t1, zero
+# CHECK-OBJ: zext.h t0, t1
+# CHECK-ASM: encoding: [0xb3,0x42,0x03,0x08]
+pack t0, t1, x0
+# CHECK-ASM-AND-OBJ: packh t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x08]
+packh t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: brev8 t0, t1
+# CHECK-ASM: encoding: [0x93,0x52,0x73,0x68]
+brev8 t0, t1
diff --git a/llvm/test/MC/RISCV/rv32zbp-aliases-valid.s b/llvm/test/MC/RISCV/rv32zbp-aliases-valid.s
index dd14f49840a06..6472394cee260 100644
--- a/llvm/test/MC/RISCV/rv32zbp-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rv32zbp-aliases-valid.s
@@ -39,7 +39,7 @@ rev4.b x5, x6
# CHECK-S-OBJ: rev2.b t0, t1
rev2.b x5, x6
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 7
+# CHECK-S-OBJ-NOALIAS: brev8 t0, t1
# CHECK-S-OBJ: rev.b t0, t1
rev.b x5, x6
@@ -151,14 +151,6 @@ zip2 x5, x6
# CHECK-S-OBJ: unzip2 t0, t1
unzip2 x5, x6
-# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 15
-# CHECK-S-OBJ: zip t0, t1
-zip x5, x6
-
-# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 15
-# CHECK-S-OBJ: unzip t0, t1
-unzip x5, x6
-
# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 1
# CHECK-S-OBJ: orc.p t0, t1
orc.p x5, x6
diff --git a/llvm/test/MC/RISCV/rv32zbp-only-valid.s b/llvm/test/MC/RISCV/rv32zbp-only-valid.s
index a7aba5ee258f6..42f462e98a21a 100644
--- a/llvm/test/MC/RISCV/rv32zbp-only-valid.s
+++ b/llvm/test/MC/RISCV/rv32zbp-only-valid.s
@@ -13,3 +13,9 @@ pack t0, t1, x0
# CHECK-OBJ: rev8 t0, t1
# CHECK-ASM: encoding: [0x93,0x52,0x83,0x69]
grevi t0, t1, 24
+# CHECK-ASM-AND-OBJ: zip t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0xf3,0x08]
+zip x5, x6
+# CHECK-ASM-AND-OBJ: unzip t0, t1
+# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x08]
+unzip x5, x6
diff --git a/llvm/test/MC/RISCV/rv32zbp-valid.s b/llvm/test/MC/RISCV/rv32zbp-valid.s
index 32474d0ead90c..5cb23fc38b242 100644
--- a/llvm/test/MC/RISCV/rv32zbp-valid.s
+++ b/llvm/test/MC/RISCV/rv32zbp-valid.s
@@ -54,5 +54,5 @@ xperm.n t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x28]
xperm.b t0, t1, t2
# CHECK-ASM-AND-OBJ: xperm.h t0, t1, t2
-# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x28
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x28]
xperm.h t0, t1, t2
diff --git a/llvm/test/MC/RISCV/rv64-zbkb-valid.s b/llvm/test/MC/RISCV/rv64-zbkb-valid.s
new file mode 100644
index 0000000000000..01e1f6a760c89
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64-zbkb-valid.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbkb < %s \
+# RUN: | llvm-objdump --mattr=+zbkb -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: rorw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x60]
+rorw t0, t1, t2
+# CHECK-ASM-AND-OBJ: rolw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x60]
+rolw t0, t1, t2
+# CHECK-ASM-AND-OBJ: roriw t0, t1, 31
+# CHECK-ASM: encoding: [0x9b,0x52,0xf3,0x61]
+roriw t0, t1, 31
+# CHECK-ASM-AND-OBJ: roriw t0, t1, 0
+# CHECK-ASM: encoding: [0x9b,0x52,0x03,0x60]
+roriw t0, t1, 0
+
+# CHECK-ASM-AND-OBJ: packw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x42,0x73,0x08]
+packw t0, t1, t2
diff --git a/llvm/test/MC/RISCV/rv64zbkb-only-valid.s b/llvm/test/MC/RISCV/rv64zbkb-only-valid.s
new file mode 100644
index 0000000000000..2d3e7381b3560
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zbkb-only-valid.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbkb -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbkb < %s \
+# RUN: | llvm-objdump --mattr=+zbkb -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: rev8 t0, t1
+# CHECK-ASM: encoding: [0x93,0x52,0x83,0x6b]
+rev8 t0, t1
diff --git a/llvm/test/MC/RISCV/rv64zbp-aliases-valid.s b/llvm/test/MC/RISCV/rv64zbp-aliases-valid.s
index 6c51d96ab6b13..c1474afec5271 100644
--- a/llvm/test/MC/RISCV/rv64zbp-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rv64zbp-aliases-valid.s
@@ -39,7 +39,7 @@ rev4.b x5, x6
# CHECK-S-OBJ: rev2.b t0, t1
rev2.b x5, x6
-# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 7
+# CHECK-S-OBJ-NOALIAS: brev8 t0, t1
# CHECK-S-OBJ: rev.b t0, t1
rev.b x5, x6
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