[PATCH] D117831: [AVR] Remove regalloc workaround for LDDWRdPtrQ
Ayke via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 20 12:59:17 PST 2022
aykevl created this revision.
aykevl added reviewers: dylanmckay, benshi001.
Herald added subscribers: Jim, JDevlieghere, hiraditya.
aykevl requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.
Background: https://github.com/avr-rust/rust-legacy-fork/issues/126
In short, this workaround was introduced to fix a "ran out of registers
during regalloc" issue. The root cause has since been fixed in
https://reviews.llvm.org/D54218 so this workaround can be removed.
There is one test that changes a little bit, removing a single
instruction. I also compiled compiler-rt before and after this patch but
didn't see a difference. So presumably the impact is very low. Still,
it's nice to be able to remove such a workaround.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D117831
Files:
llvm/lib/Target/AVR/AVRInstrInfo.td
llvm/lib/Target/AVR/AVRRegisterInfo.td
llvm/test/CodeGen/AVR/lpmx.ll
Index: llvm/test/CodeGen/AVR/lpmx.ll
===================================================================
--- llvm/test/CodeGen/AVR/lpmx.ll
+++ llvm/test/CodeGen/AVR/lpmx.ll
@@ -22,13 +22,12 @@
; CHECK-O0-NEXT: out 61, r28
; CHECK-O0-NEXT: std Y+1, r24
; CHECK-O0-NEXT: std Y+2, r25
-; CHECK-O0-NEXT: ldd r24, Y+1
-; CHECK-O0-NEXT: ldd r25, Y+2
-; CHECK-O0-NEXT: lsl r24
-; CHECK-O0-NEXT: rol r25
-; CHECK-O0-NEXT: subi r24, -lo8(arr0)
-; CHECK-O0-NEXT: sbci r25, -hi8(arr0)
-; CHECK-O0-NEXT: movw r30, r24
+; CHECK-O0-NEXT: ldd r30, Y+1
+; CHECK-O0-NEXT: ldd r31, Y+2
+; CHECK-O0-NEXT: lsl r30
+; CHECK-O0-NEXT: rol r31
+; CHECK-O0-NEXT: subi r30, -lo8(arr0)
+; CHECK-O0-NEXT: sbci r31, -hi8(arr0)
; CHECK-O0-NEXT: lpm r24, Z+
; CHECK-O0-NEXT: lpm r25, Z
; CHECK-O0-NEXT: adiw r28, 2
@@ -95,11 +94,10 @@
; CHECK-O0-NEXT: out 61, r28
; CHECK-O0-NEXT: std Y+1, r24
; CHECK-O0-NEXT: std Y+2, r25
-; CHECK-O0-NEXT: ldd r24, Y+1
-; CHECK-O0-NEXT: ldd r25, Y+2
-; CHECK-O0-NEXT: subi r24, -lo8(arr1)
-; CHECK-O0-NEXT: sbci r25, -hi8(arr1)
-; CHECK-O0-NEXT: movw r30, r24
+; CHECK-O0-NEXT: ldd r30, Y+1
+; CHECK-O0-NEXT: ldd r31, Y+2
+; CHECK-O0-NEXT: subi r30, -lo8(arr1)
+; CHECK-O0-NEXT: sbci r31, -hi8(arr1)
; CHECK-O0-NEXT: lpm r24, Z
; CHECK-O0-NEXT: adiw r28, 2
; CHECK-O0-NEXT: in r0, 63
Index: llvm/lib/Target/AVR/AVRRegisterInfo.td
===================================================================
--- llvm/lib/Target/AVR/AVRRegisterInfo.td
+++ llvm/lib/Target/AVR/AVRRegisterInfo.td
@@ -186,26 +186,6 @@
// allow r30 or r31 as output operands.
def DREGSLPM : RegisterClass<"AVR", [i16], 8, (sub DREGS, R31R30)>;
-// The 16-bit DREGS register class, excluding the Z pointer register.
-//
-// This is used by instructions which cause high pointer register
-// contention which leads to an assertion in the register allocator.
-//
-// There is no technical reason why instructions that use this class
-// cannot use Z; it's simply a workaround a regalloc bug.
-//
-// More information can be found in PR39553.
-def DREGS_WITHOUT_YZ_WORKAROUND
- : RegisterClass<"AVR", [i16], 8,
- (
- // Return value and arguments.
- add R25R24, R19R18, R21R20, R23R22,
- // Scratch registers.
- R27R26,
- // Callee saved registers.
- R17R16, R15R14, R13R12, R11R10, R9R8, R7R6, R5R4, R3R2,
- R1R0)>;
-
// 16-bit register class for immediate instructions.
def DLDREGS : RegisterClass<"AVR", [i16], 8,
(
Index: llvm/lib/Target/AVR/AVRInstrInfo.td
===================================================================
--- llvm/lib/Target/AVR/AVRInstrInfo.td
+++ llvm/lib/Target/AVR/AVRInstrInfo.td
@@ -1394,7 +1394,7 @@
// ldd Rd, P+q
// ldd Rd+1, P+q+1
let Constraints = "@earlyclobber $dst" in def LDDWRdPtrQ
- : Pseudo<(outs DREGS_WITHOUT_YZ_WORKAROUND
+ : Pseudo<(outs DREGS
: $dst),
(ins memri
: $memri),
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