[PATCH] D112986: [Clang][RISCV] Restrict rvv builtin-s with zve macro-s

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:149
   RV64 = 1 << 5,
+  VectorMaxELen32 = 1 << 6,
+  VectorMaxELen64 = 1 << 7,
----------------
Do we need VectorMaxELen32 isn't that the minimum?


================
Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:804
+      RISCVPredefinedMacros |= RISCVPredefinedMacro::Zfh;
     else if (T->isFloatVector(32) || T->isFloat(32))
+      RISCVPredefinedMacros |= RISCVPredefinedMacro::F;
----------------
Can D and F go away?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112986/new/

https://reviews.llvm.org/D112986