[PATCH] D116864: [RISCV] Add DAG combine to fold (fp_to_int_sat (ffloor X)) -> (select X == nan, 0, (fcvt X, rdn))
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 20 11:38:43 PST 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG94e69fbb4f3a: [RISCV] Add DAG combine to fold (fp_to_int_sat (ffloor X)) -> (select X == nan… (authored by craig.topper).
Changed prior to commit:
https://reviews.llvm.org/D116864?vs=398353&id=401723#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D116864/new/
https://reviews.llvm.org/D116864
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D116864.401723.patch
Type: text/x-patch
Size: 100342 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220120/8aeda5cc/attachment.bin>
More information about the llvm-commits
mailing list