[llvm] 9abc593 - [TargetLowering][InstCombine] Simplify BSwap demanded bits code a little. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 20 10:45:26 PST 2022
Author: Craig Topper
Date: 2022-01-20T10:45:17-08:00
New Revision: 9abc593e98891b4cd8ffd2ca308cabe6ea5d142f
URL: https://github.com/llvm/llvm-project/commit/9abc593e98891b4cd8ffd2ca308cabe6ea5d142f
DIFF: https://github.com/llvm/llvm-project/commit/9abc593e98891b4cd8ffd2ca308cabe6ea5d142f.diff
LOG: [TargetLowering][InstCombine] Simplify BSwap demanded bits code a little. NFC
Use alignDown instead of &= ~7.
Replace ResultBit with NLZ. (BitWidth - NLZ - NTZ == 8) so
(BitWidth - NTZ - 8 == NLZ).
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D117804
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 6af5609993795..3b53a5b8b7532 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1815,20 +1815,16 @@ bool TargetLowering::SimplifyDemandedBits(
// Round NTZ down to the next byte. If we have 11 trailing zeros, then
// we need all the bits down to bit 8. Likewise, round NLZ. If we
// have 14 leading zeros, round to 8.
- NLZ &= ~7;
- NTZ &= ~7;
+ NLZ = alignDown(NLZ, 8);
+ NTZ = alignDown(NTZ, 8);
// If we need exactly one byte, we can do this transformation.
if (BitWidth - NLZ - NTZ == 8) {
- unsigned ResultBit = NTZ;
- unsigned InputBit = BitWidth - NTZ - 8;
-
// Replace this with either a left or right shift to get the byte into
// the right place.
- unsigned ShiftOpcode = InputBit > ResultBit ? ISD::SRL : ISD::SHL;
+ unsigned ShiftOpcode = NLZ > NTZ ? ISD::SRL : ISD::SHL;
if (!TLO.LegalOperations() || isOperationLegal(ShiftOpcode, VT)) {
EVT ShiftAmtTy = getShiftAmountTy(VT, DL);
- unsigned ShiftAmount =
- InputBit > ResultBit ? InputBit - ResultBit : ResultBit - InputBit;
+ unsigned ShiftAmount = NLZ > NTZ ? NLZ - NTZ : NTZ - NLZ;
SDValue ShAmt = TLO.DAG.getConstant(ShiftAmount, dl, ShiftAmtTy);
SDValue NewOp = TLO.DAG.getNode(ShiftOpcode, dl, VT, Src, ShAmt);
return TLO.CombineTo(Op, NewOp);
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index 4dc712f325362..71a5ae24eead9 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -800,22 +800,21 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
// Round NTZ down to the next byte. If we have 11 trailing zeros, then
// we need all the bits down to bit 8. Likewise, round NLZ. If we
// have 14 leading zeros, round to 8.
- NLZ &= ~7;
- NTZ &= ~7;
+ NLZ = alignDown(NLZ, 8);
+ NTZ = alignDown(NTZ, 8);
// If we need exactly one byte, we can do this transformation.
- if (BitWidth-NLZ-NTZ == 8) {
- unsigned ResultBit = NTZ;
- unsigned InputBit = BitWidth-NTZ-8;
-
+ if (BitWidth - NLZ - NTZ == 8) {
// Replace this with either a left or right shift to get the byte into
// the right place.
Instruction *NewVal;
- if (InputBit > ResultBit)
- NewVal = BinaryOperator::CreateLShr(II->getArgOperand(0),
- ConstantInt::get(I->getType(), InputBit-ResultBit));
+ if (NLZ > NTZ)
+ NewVal = BinaryOperator::CreateLShr(
+ II->getArgOperand(0),
+ ConstantInt::get(I->getType(), NLZ - NTZ));
else
- NewVal = BinaryOperator::CreateShl(II->getArgOperand(0),
- ConstantInt::get(I->getType(), ResultBit-InputBit));
+ NewVal = BinaryOperator::CreateShl(
+ II->getArgOperand(0),
+ ConstantInt::get(I->getType(), NTZ - NLZ));
NewVal->takeName(I);
return InsertNewInstWith(NewVal, *I);
}
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