[PATCH] D117789: [RISCV] Add support for Zihintpause extention

[Shao-Ce SUN via Phabricator via llvm-commits]

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Add support for the 'pause' hint instruction as an alias for
'fence w, 0'. To do this allow the 'fence' operands pred and succ
to be set to 0 (the empty set). This will also allow future hints
to be encoded as 'fence 0, <x>' and 'fence <x>, 0'.

This patch revised from @mundaym's D93019 <https://reviews.llvm.org/D93019>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117789

Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/Disassembler/RISCV/unknown-fence-field.txt
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zihintpause-valid.s
  llvm/test/MC/RISCV/rvzihintpause-aliases-valid.s

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