[PATCH] D117680: [InstCombine] Simplify bswap -> shift

Thu Jan 20 07:23:07 PST 2022

chfast added a comment.

In D117680#3255155 <https://reviews.llvm.org/D117680#3255155>, @craig.topper wrote:

> Can we do computeKnownBits().countMaxActiveBits() <= 8 -> replace with shl. If (BitWidth - computeKnownBits().countMaxTrailingZeros()) <= 8 -> replace with lshr?

I did this, except I used `BitWidth - computeKnownBits().countMinTrailingZeros()` witch I believe is the correct one.

================
Comment at: llvm/test/Transforms/InstCombine/bswap-fold.ll:421
+;
+  %2 = shl <2 x i64> %0, <i64 56, i64 undef>
+  %3 = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %2)
----------------
Any `undef` shift index or `and` argument prevents this optimization. Is this expected?

================
Comment at: llvm/test/Transforms/InstCombine/bswap-fold.ll:442
+; CHECK-NEXT:    [[TMP2:%.*]] = shl i64 [[TMP0:%.*]], 57
+; CHECK-NEXT:    [[TMP3:%.*]] = shl i64 [[TMP0]], 1
+; CHECK-NEXT:    [[TMP4:%.*]] = and i64 [[TMP3]], 254
----------------
Here we replace bswap with `lshr i64 %2, 56`, but it is further expanded to 
```
shl i64 %0, 1
and i64 %3, 254
```

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D117680/new/

https://reviews.llvm.org/D117680