[PATCH] D117755: [AArch64] Remove PRBAR0_ELn and PRLAR0_ELn sysregs.

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham created this revision.
simon_tatham added reviewers: labrinea, john.brawn, ostannard, miyuki.
Herald added subscribers: hiraditya, kristof.beyls.
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The Armv8-R.64 architecture defines numbered MPU region registers with
indices 1-15, not 0-15. So there's no such register as PRBAR0_EL2 or
PRLAR0_EL1 (for example). The encodings that they would occupy are
used for the unnumbered PRBAR_ELn and PRLAR_ELn registers.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117755

Files:
  llvm/lib/Target/AArch64/AArch64SystemOperands.td
  llvm/test/MC/AArch64/armv8r-sysreg.s
  llvm/test/MC/Disassembler/AArch64/armv8r-sysreg.txt

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