[PATCH] D116580: [M68k] Add addressing modes ARIPI and ARIPD support for BTST

Wed Jan 19 21:36:40 PST 2022

Jim marked an inline comment as done.
Jim added a comment.

================
Comment at: llvm/test/MC/M68k/Bits/Classes/MxBTST_MI.s:15
+; CHECK-SAME: encoding: [0x08,0x18,0x00,0xff]
+btst	#-1, (%a0)+
+
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ricky26 wrote:
> I'm not sure whether this is defined behaviour. The spec I have says that BTST with a register for the bit number wraps, but doesn't specify that behaviour for the immediate mode, so it probably works. Additionally, I don't think it would be signed, but again, I suspect it'll still work (-1 will be interpreted as 31).
The spec for BTST mentioned `When a data register is the destination, any of the 32 bits can be specified by a modulo 32- bit number. When a memory location is the destination, the operation is a byte operation, and the bit number is modulo 8.`  

Maybe have another revision to forbid signed number as immediate operand in the future.

The reference spec: https://www.nxp.com/files-static/archives/doc/ref_manual/M68000PRM.pdf

Repository:
  rG LLVM Github Monorepo

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