[llvm] 21c79be - [RISCV] Add patterns to MIR sign-extension removal pass.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 19 17:34:05 PST 2022
Author: Mohammed Nurul Hoque
Date: 2022-01-19T17:33:58-08:00
New Revision: 21c79be5d7a388fa1f304412b1a9aba123f8dbde
URL: https://github.com/llvm/llvm-project/commit/21c79be5d7a388fa1f304412b1a9aba123f8dbde
DIFF: https://github.com/llvm/llvm-project/commit/21c79be5d7a388fa1f304412b1a9aba123f8dbde.diff
LOG: [RISCV] Add patterns to MIR sign-extension removal pass.
This patch adds a few instruction patterns that generate sign-extended values or propagate them, adding to the pass introduced in https://reviews.llvm.org/D116397
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D117465
Added:
Modified:
llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
llvm/test/CodeGen/RISCV/sextw-removal.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
index c7df709be5f5b..12ec52925798f 100644
--- a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
@@ -95,24 +95,32 @@ static bool isSignExtendingOpW(const MachineInstr &MI) {
case RISCV::LHU:
case RISCV::LB:
case RISCV::LH:
+ case RISCV::SLT:
+ case RISCV::SLTI:
+ case RISCV::SLTU:
+ case RISCV::SLTIU:
case RISCV::SEXTB:
case RISCV::SEXTH:
case RISCV::ZEXTH_RV64:
return true;
- }
-
+ // shifting right sufficiently makes the value 32-bit sign-extended
+ case RISCV::SRAI:
+ return MI.getOperand(2).getImm() >= 32;
+ case RISCV::SRLI:
+ return MI.getOperand(2).getImm() > 32;
// The LI pattern ADDI rd, X0, imm is sign extended.
- if (MI.getOpcode() == RISCV::ADDI && MI.getOperand(1).isReg() &&
- MI.getOperand(1).getReg() == RISCV::X0)
- return true;
-
+ case RISCV::ADDI:
+ return MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0;
// An ANDI with an 11 bit immediate will zero bits 63:11.
- if (MI.getOpcode() == RISCV::ANDI && isUInt<11>(MI.getOperand(2).getImm()))
- return true;
-
+ case RISCV::ANDI:
+ return isUInt<11>(MI.getOperand(2).getImm());
+ // An ORI with an >11 bit immediate (negative 12-bit) will set bits 63:11.
+ case RISCV::ORI:
+ return !isUInt<11>(MI.getOperand(2).getImm());
// Copying from X0 produces zero.
- if (MI.getOpcode() == RISCV::COPY && MI.getOperand(1).getReg() == RISCV::X0)
- return true;
+ case RISCV::COPY:
+ return MI.getOperand(1).getReg() == RISCV::X0;
+ }
return false;
}
@@ -157,9 +165,12 @@ static bool isSignExtendedW(const MachineInstr &OrigMI,
Worklist.push_back(SrcMI);
break;
}
+ case RISCV::REM:
case RISCV::ANDI:
case RISCV::ORI:
case RISCV::XORI: {
+ // |Remainder| is always <= |Dividend|. If D is 32-bit, then so is R.
+ // DIV doesn't work because of the edge case 0xf..f 8000 0000 / (long)-1
// Logical operations use a sign extended 12-bit immediate. We just need
// to check if the other operand is sign extended.
Register SrcReg = MI->getOperand(1).getReg();
@@ -173,6 +184,7 @@ static bool isSignExtendedW(const MachineInstr &OrigMI,
Worklist.push_back(SrcMI);
break;
}
+ case RISCV::REMU:
case RISCV::AND:
case RISCV::OR:
case RISCV::XOR:
diff --git a/llvm/test/CodeGen/RISCV/sextw-removal.ll b/llvm/test/CodeGen/RISCV/sextw-removal.ll
index 753e0b0acafc4..868ab46acedc0 100644
--- a/llvm/test/CodeGen/RISCV/sextw-removal.ll
+++ b/llvm/test/CodeGen/RISCV/sextw-removal.ll
@@ -316,3 +316,106 @@ bb7: ; preds = %bb2
ret void
}
declare float @baz(i32 signext %i3)
+
+define void @test8(i32 signext %arg, i32 signext %arg1) nounwind {
+; CHECK-LABEL: test8:
+; CHECK: # %bb.0: # %bb
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sraw a0, a0, a1
+; CHECK-NEXT: .LBB6_1: # %bb2
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: call foo at plt
+; CHECK-NEXT: ori a0, a0, -256
+; CHECK-NEXT: bnez a0, .LBB6_1
+; CHECK-NEXT: # %bb.2: # %bb7
+; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: ret
+;
+; NOREMOVAL-LABEL: test8:
+; NOREMOVAL: # %bb.0: # %bb
+; NOREMOVAL-NEXT: addi sp, sp, -16
+; NOREMOVAL-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; NOREMOVAL-NEXT: sraw a0, a0, a1
+; NOREMOVAL-NEXT: .LBB6_1: # %bb2
+; NOREMOVAL-NEXT: # =>This Inner Loop Header: Depth=1
+; NOREMOVAL-NEXT: sext.w a0, a0
+; NOREMOVAL-NEXT: call foo at plt
+; NOREMOVAL-NEXT: ori a0, a0, -256
+; NOREMOVAL-NEXT: bnez a0, .LBB6_1
+; NOREMOVAL-NEXT: # %bb.2: # %bb7
+; NOREMOVAL-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; NOREMOVAL-NEXT: addi sp, sp, 16
+; NOREMOVAL-NEXT: ret
+bb:
+ %i = ashr i32 %arg, %arg1
+ br label %bb2
+
+bb2: ; preds = %bb2, %bb
+ %i3 = phi i32 [ %i, %bb ], [ %i6, %bb2 ]
+ %i4 = tail call signext i64 @foo(i32 signext %i3)
+ %i5 = or i64 %i4, -256
+ %i6 = trunc i64 %i5 to i32
+ %i7 = icmp eq i32 %i6, 0
+ br i1 %i7, label %bb7, label %bb2
+
+bb7: ; preds = %bb2
+ ret void
+}
+
+declare i64 @foo(i32 signext)
+
+define void @test9(i32 signext %arg, i32 signext %arg1) nounwind {
+; CHECK-LABEL: test9:
+; CHECK: # %bb.0: # %bb
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sraw a0, a0, a1
+; CHECK-NEXT: li s0, 254
+; CHECK-NEXT: .LBB7_1: # %bb2
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: call bar at plt
+; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: slti a0, a0, 255
+; CHECK-NEXT: blt s0, a1, .LBB7_1
+; CHECK-NEXT: # %bb.2: # %bb7
+; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: ret
+;
+; NOREMOVAL-LABEL: test9:
+; NOREMOVAL: # %bb.0: # %bb
+; NOREMOVAL-NEXT: addi sp, sp, -16
+; NOREMOVAL-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; NOREMOVAL-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
+; NOREMOVAL-NEXT: sraw a1, a0, a1
+; NOREMOVAL-NEXT: li s0, 254
+; NOREMOVAL-NEXT: .LBB7_1: # %bb2
+; NOREMOVAL-NEXT: # =>This Inner Loop Header: Depth=1
+; NOREMOVAL-NEXT: sext.w a0, a1
+; NOREMOVAL-NEXT: call bar at plt
+; NOREMOVAL-NEXT: slti a1, a0, 255
+; NOREMOVAL-NEXT: blt s0, a0, .LBB7_1
+; NOREMOVAL-NEXT: # %bb.2: # %bb7
+; NOREMOVAL-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; NOREMOVAL-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
+; NOREMOVAL-NEXT: addi sp, sp, 16
+; NOREMOVAL-NEXT: ret
+bb:
+ %i = ashr i32 %arg, %arg1
+ br label %bb2
+
+bb2: ; preds = %bb2, %bb
+ %i3 = phi i32 [ %i, %bb ], [ %i7, %bb2 ]
+ %i4 = tail call signext i32 @bar(i32 signext %i3)
+ %i5 = icmp slt i32 %i4, 255
+ %i6 = sext i1 %i5 to i32
+ %i7 = sub i32 0, %i6
+ br i1 %i5, label %bb7, label %bb2
+
+bb7: ; preds = %bb2
+ ret void
+}
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