[PATCH] D117681: [RISCV] Add the policy operand for some masked RVV ternary IR intrinsics.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:2187
+multiclass VPseudoTernaryNoMaskNoPolicy<VReg RetClass,
+                          RegisterClass Op1Class,
+                          DAGOperand Op2Class,
----------------
Ident the other arguments to line up with the first argument


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117681/new/

https://reviews.llvm.org/D117681