[PATCH] D116053: [MachineSink] Allow sinking of constant or ignorable physreg uses

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

Another, shorter, approach may be:

  diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  index 88996f455227..f85a71941e66 100644
  --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  @@ -132,8 +132,10 @@ bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
  
   bool SIInstrInfo::isIgnorableUse(const MachineOperand &MO) const {
     // Any implicit use of exec by VALU is not a real register read.
  +  // isRematerializable check excludes instructions reading EXEC as data,
  +  // such as compares, v_cndmask_b32, and readfirstlane.
     return MO.getReg() == AMDGPU::EXEC && MO.isImplicit() &&
  -         isVALU(*MO.getParent());
  +         isVALU(*MO.getParent()) && MO.getParent()->isRematerializable();
   }
  
   bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,


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https://reviews.llvm.org/D116053