[llvm] 5fa826f - [RISCV] Test expected inst opcode in sink-splat test

[Fraser Cormack via llvm-commits]

Author: Fraser Cormack
Date: 2022-01-19T17:18:24Z
New Revision: 5fa826f4e284db6a3647d8aa823707da3275ae14

URL: https://github.com/llvm/llvm-project/commit/5fa826f4e284db6a3647d8aa823707da3275ae14
DIFF: https://github.com/llvm/llvm-project/commit/5fa826f4e284db6a3647d8aa823707da3275ae14.diff

LOG: [RISCV] Test expected inst opcode in sink-splat test

The function's name suggests it should be testing 'sub' rather than
'add'. We test 'add' in an earlier test so we're not losing any coverage
here.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
index b44088aa6f75a..7f4d2ec0b8f1e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
@@ -82,7 +82,7 @@ define void @sink_splat_sub(i32* nocapture %a, i32 signext %x) {
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
 ; CHECK-NEXT:    vle32.v v8, (a0)
-; CHECK-NEXT:    vadd.vx v8, v8, a1
+; CHECK-NEXT:    vsub.vx v8, v8, a1
 ; CHECK-NEXT:    vse32.v v8, (a0)
 ; CHECK-NEXT:    addi a2, a2, -4
 ; CHECK-NEXT:    addi a0, a0, 16
@@ -99,7 +99,7 @@ vector.body:                                      ; preds = %vector.body, %entry
   %0 = getelementptr inbounds i32, i32* %a, i64 %index
   %1 = bitcast i32* %0 to <4 x i32>*
   %wide.load = load <4 x i32>, <4 x i32>* %1, align 4
-  %2 = add <4 x i32> %wide.load, %broadcast.splat
+  %2 = sub <4 x i32> %wide.load, %broadcast.splat
   %3 = bitcast i32* %0 to <4 x i32>*
   store <4 x i32> %2, <4 x i32>* %3, align 4
   %index.next = add nuw i64 %index, 4