[PATCH] D117643: [RISCV] Add patterns for vector widening integer reduction instructions

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

It'd be nice to see this work for fixed vectors too as I'm concerned we're starting to diverge in support between this and other recent patches, but I suppose we'd need extra patterns for the `riscv_sext_vl` and `riscv_zext_vl`, right?



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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:651
+    defvar wti_m1 = !cast<VTypeInfo>("VI"#wti.SEW#"M1");
+    def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge),
+                                 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1))),
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The "true mask" case isn't tested by this patch.


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  https://reviews.llvm.org/D117643/new/

https://reviews.llvm.org/D117643