[llvm] 63eea41 - [AMDGPU] Simplify SILoadStoreOptimizer::getSubRegIdxs. NFC.

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2022-01-19T15:20:35Z
New Revision: 63eea41de63ac33decd43bc21c24fb848619732e

URL: https://github.com/llvm/llvm-project/commit/63eea41de63ac33decd43bc21c24fb848619732e
DIFF: https://github.com/llvm/llvm-project/commit/63eea41de63ac33decd43bc21c24fb848619732e.diff

LOG: [AMDGPU] Simplify SILoadStoreOptimizer::getSubRegIdxs. NFC.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
index 4f807cca00eb..48f6c7ef1bca 100644
--- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
@@ -1542,49 +1542,36 @@ unsigned SILoadStoreOptimizer::getNewOpcode(const CombineInfo &CI,
 std::pair<unsigned, unsigned>
 SILoadStoreOptimizer::getSubRegIdxs(const CombineInfo &CI,
                                     const CombineInfo &Paired) {
-
-  assert(CI.Width != 0 && Paired.Width != 0 && "Width cannot be zero");
-
   bool ReverseOrder;
   if (CI.InstClass == MIMG) {
     assert(
         (countPopulation(CI.DMask | Paired.DMask) == CI.Width + Paired.Width) &&
         "No overlaps");
     ReverseOrder = CI.DMask > Paired.DMask;
-  } else
+  } else {
     ReverseOrder = CI.Offset > Paired.Offset;
+  }
 
   unsigned Idx0;
   unsigned Idx1;
 
-  if (CI.Width + Paired.Width > 4) {
-    assert(CI.Width == 4 && Paired.Width == 4);
+  static const unsigned Idxs[5][4] = {
+      {AMDGPU::sub0, AMDGPU::sub0_sub1, AMDGPU::sub0_sub1_sub2, AMDGPU::sub0_sub1_sub2_sub3},
+      {AMDGPU::sub1, AMDGPU::sub1_sub2, AMDGPU::sub1_sub2_sub3, AMDGPU::sub1_sub2_sub3_sub4},
+      {AMDGPU::sub2, AMDGPU::sub2_sub3, AMDGPU::sub2_sub3_sub4, AMDGPU::sub2_sub3_sub4_sub5},
+      {AMDGPU::sub3, AMDGPU::sub3_sub4, AMDGPU::sub3_sub4_sub5, AMDGPU::sub3_sub4_sub5_sub6},
+      {AMDGPU::sub4, AMDGPU::sub4_sub5, AMDGPU::sub4_sub5_sub6, AMDGPU::sub4_sub5_sub6_sub7},
+  };
 
-    if (ReverseOrder) {
-      Idx1 = AMDGPU::sub0_sub1_sub2_sub3;
-      Idx0 = AMDGPU::sub4_sub5_sub6_sub7;
-    } else {
-      Idx0 = AMDGPU::sub0_sub1_sub2_sub3;
-      Idx1 = AMDGPU::sub4_sub5_sub6_sub7;
-    }
+  assert(CI.Width >= 1 && CI.Width <= 4);
+  assert(Paired.Width >= 1 && Paired.Width <= 4);
+
+  if (ReverseOrder) {
+    Idx1 = Idxs[0][Paired.Width - 1];
+    Idx0 = Idxs[Paired.Width][CI.Width - 1];
   } else {
-    static const unsigned Idxs[4][4] = {
-        {AMDGPU::sub0, AMDGPU::sub0_sub1, AMDGPU::sub0_sub1_sub2, AMDGPU::sub0_sub1_sub2_sub3},
-        {AMDGPU::sub1, AMDGPU::sub1_sub2, AMDGPU::sub1_sub2_sub3, 0},
-        {AMDGPU::sub2, AMDGPU::sub2_sub3, 0, 0},
-        {AMDGPU::sub3, 0, 0, 0},
-    };
-
-    assert(CI.Width >= 1 && CI.Width <= 3);
-    assert(Paired.Width >= 1 && Paired.Width <= 3);
-
-    if (ReverseOrder) {
-      Idx1 = Idxs[0][Paired.Width - 1];
-      Idx0 = Idxs[Paired.Width][CI.Width - 1];
-    } else {
-      Idx0 = Idxs[0][CI.Width - 1];
-      Idx1 = Idxs[CI.Width][Paired.Width - 1];
-    }
+    Idx0 = Idxs[0][CI.Width - 1];
+    Idx1 = Idxs[CI.Width][Paired.Width - 1];
   }
 
   return std::make_pair(Idx0, Idx1);