[PATCH] D116915: [DAGCombiner][AArch64] Enhance to support for scalar CSINC

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Some of the previous comments don't appear to have been addressed. Only looking for a CopyFromReg looks suspicious, and there is no testing for csneg that I can see.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14627
+  ConstantSDNode *CC = cast<ConstantSDNode>(CCVal);
+  assert((CC->isOne() || CC->isZero()) && "Unexpected constant vluae");
+
----------------
I don't think this will only be EQ or NE. It can be any of the predicates.

The condition code is usually obtained via `static_cast<AArch64CC::CondCode>(OpCC->getZExtValue())` or something like it.


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https://reviews.llvm.org/D116915