[PATCH] D114800: [PowerPC] Replace MFVSRLD with MFVSRD when the vector is symmetrical

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf added a comment.

In D114800#3197765 <https://reviews.llvm.org/D114800#3197765>, @stefanp wrote:

> In D114800#3163072 <https://reviews.llvm.org/D114800#3163072>, @shchenz wrote:
>
>> Can we fix this at the place where `MFVSRLD` is generated? (in DAG-ISEL?)
>
> I see what you mean. This can be done in DAG-ISEL. 
> However, there are a couple of reasons why I chose to do this here.
>
> 1. I think it is easier to do here and the code is simpler to understand. We are looking to replace `MFVSRLD` so we just look for that instruction and then replace it. In DAG ISEL we would have to first figure out which extract element node eventually gets turned into this instruction and then see if it can be replaced.
> 2. There are situations where the choice of preceding instructions matters to whether or not we can use the other doubleword. Again, it would be a situation where we would have to figure out what a node is turned into before deciding if the doubleword is symmetrical.

Will putting code in post-isel peephole help? See D97658 <https://reviews.llvm.org/D97658>.


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