[llvm] b3a0ec7 - [RISCV] Remove DemandedBits handling for FSR/FSL until we have test cases for it.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-01-18T10:52:43-08:00
New Revision: b3a0ec7645dbd2978bd43f372933d1d1cd36f132

URL: https://github.com/llvm/llvm-project/commit/b3a0ec7645dbd2978bd43f372933d1d1cd36f132
DIFF: https://github.com/llvm/llvm-project/commit/b3a0ec7645dbd2978bd43f372933d1d1cd36f132.diff

LOG: [RISCV] Remove DemandedBits handling for FSR/FSL until we have test cases for it.

Testing may be easier after D117468. Right now we get demanded bits
optimizations done on ISD::FSHL/FSHR before they become FSR/FSL. This
makes it hard to test.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 39ecf0a3dbedf..0f8e21914e30b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -7273,25 +7273,6 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
       return SDValue(N, 0);
     break;
   }
-  case RISCVISD::FSL:
-  case RISCVISD::FSR: {
-    // Only the lower log2(Bitwidth)+1 bits of the the shift amount are read.
-    unsigned BitWidth = N->getOperand(2).getValueSizeInBits();
-    assert(isPowerOf2_32(BitWidth) && "Unexpected bit width");
-    if (SimplifyDemandedLowBitsHelper(2, Log2_32(BitWidth) + 1))
-      return SDValue(N, 0);
-    break;
-  }
-  case RISCVISD::FSLW:
-  case RISCVISD::FSRW: {
-    // Only the lower 32 bits of Values and lower 6 bits of shift amount are
-    // read.
-    if (SimplifyDemandedLowBitsHelper(0, 32) ||
-        SimplifyDemandedLowBitsHelper(1, 32) ||
-        SimplifyDemandedLowBitsHelper(2, 6))
-      return SDValue(N, 0);
-    break;
-  }
   case RISCVISD::GREV:
   case RISCVISD::GORC: {
     // Only the lower log2(Bitwidth) bits of the the shift amount are read.