[PATCH] D117588: Pre-commit test case for trunc+lshr+load folds

[Bjorn Pettersson via Phabricator via llvm-commits]

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This is a pre-commit of test cases relevant for D117406 <https://reviews.llvm.org/D117406>.

@srl_load_narrowing1 is showing a pattern that could be folded into
a more narrow load.

@srl_load_narrowing2 is showing a similar pattern that happens to
be optimized already, but that happens in two steps (first triggering
a combine based on SRL and later another combine based on TRUNCATE).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117588

Files:
  llvm/test/CodeGen/X86/shift-folding.ll


Index: llvm/test/CodeGen/X86/shift-folding.ll
===================================================================
--- llvm/test/CodeGen/X86/shift-folding.ll
+++ llvm/test/CodeGen/X86/shift-folding.ll
@@ -83,3 +83,30 @@
   ret i32 %xor
 }
 
+; Should be possible to adjust the pointer and narrow the load to 16 bits.
+define i16 @srl_load_narrowing1(i32* %arg) {
+; CHECK-LABEL: srl_load_narrowing1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    movl (%eax), %eax
+; CHECK-NEXT:    shrl $8, %eax
+; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT:    retl
+  %tmp1 = load i32, i32* %arg, align 1
+  %tmp2 = lshr i32 %tmp1, 8
+  %tmp3 = trunc i32 %tmp2 to i16
+  ret i16 %tmp3
+}
+
+define i16 @srl_load_narrowing2(i32* %arg) {
+; CHECK-LABEL: srl_load_narrowing2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    movzbl 3(%eax), %eax
+; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT:    retl
+  %tmp1 = load i32, i32* %arg, align 1
+  %tmp2 = lshr i32 %tmp1, 24
+  %tmp3 = trunc i32 %tmp2 to i16
+  ret i16 %tmp3
+}


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