[PATCH] D93019: [RISCV] Add support for Zihintpause extention

[Shao-Ce SUN via Phabricator via llvm-commits]

achieveartificialintelligence updated this revision to Diff 400746.
achieveartificialintelligence added a comment.

This patch is accepted a year ago. Could this patch land now?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93019/new/

https://reviews.llvm.org/D93019

Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/Disassembler/RISCV/unknown-fence-field.txt
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zihintpause-valid.s
  llvm/test/MC/RISCV/rvzihintpause-aliases-valid.s

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